| Message ID | 20230731-topic-pcnoc-v1-2-452dd36d11d7@linaro.org |
|---|---|
| State | Accepted |
| Commit | e1cd74b6dccb98ca09e4612ff29c7658db7a487b |
| Headers | show |
| Series | Set PCNoC clk always-on, with or without interconnect | expand |
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index ebb8d9aac89d..0191fc0dd7da 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -455,7 +455,7 @@ DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); +DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL); DEFINE_CLK_SMD_RPM_BUS(snoc, 1); DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); DEFINE_CLK_SMD_RPM_BUS(cnoc, 2);
On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must be always-on as long as the APSS is online and only has to run at 19.2 MHz. Define it to be as such in the ACTIVE domain. Some SoCs use that clock for bus scaling, while others just need it for reaching the hardware. This commit will hurt neither. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/clk/qcom/clk-smd-rpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)