@@ -158,4 +158,16 @@ mcu_esm: esm@4100000 {
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>;
};
+
+ mcu_m4fss: m4fss@5000000 {
+ compatible = "ti,am64-m4fss";
+ reg = <0x00 0x5000000 0x00 0x30000>,
+ <0x00 0x5040000 0x00 0x10000>;
+ reg-names = "iram", "dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <9>;
+ ti,sci-proc-ids = <0x18 0xff>;
+ resets = <&k3_reset 9 1>;
+ firmware-name = "am64-mcu-m4f0_0-fw";
+ };
};
@@ -99,6 +99,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
no-map;
};
+ mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_m4fss_memory_region: m4f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
@@ -639,6 +651,12 @@ &main_r5fss1_core1 {
<&main_r5fss1_core1_memory_region>;
};
+&mcu_m4fss {
+ mboxes = <&mailbox0_cluster6>, <&mbox_m4_0>;
+ memory-region = <&mcu_m4fss_dma_memory_region>,
+ <&mcu_m4fss_memory_region>;
+};
+
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
@@ -98,6 +98,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
no-map;
};
+ mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_m4fss_memory_region: m4f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
@@ -637,6 +649,12 @@ &main_r5fss1_core1 {
<&main_r5fss1_core1_memory_region>;
};
+&mcu_m4fss {
+ mboxes = <&mailbox0_cluster6>, <&mbox_m4_0>;
+ memory-region = <&mcu_m4fss_dma_memory_region>,
+ <&mcu_m4fss_memory_region>;
+};
+
&ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J3 */
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. The first region is used as a DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each rproc device. The M4F processor do not have an MMU, and as such require the exact memory used by the firmware to be set-aside. Signed-off-by: Hari Nagalla <hnagalla@ti.com> --- Changes in v5: - Add M4F device node patches to the patch list arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 18 ++++++++++++++++++ 3 files changed, 48 insertions(+)