| Message ID | 20230831030904.1194667-3-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg: Add gvec compare with immediate and scalar operand | expand |
在 2023/8/31 上午11:09, Richard Henderson 写道: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/tcg/translate.c | 56 ++++++-------------------------------- > 1 file changed, 9 insertions(+), 47 deletions(-) > > diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c > index 38ad8dd4bd..89a7392ed3 100644 > --- a/target/arm/tcg/translate.c > +++ b/target/arm/tcg/translate.c Reviewed-by: Song Gao <gaosong@loongson.cn> Thanks. Song Gao > @@ -2943,54 +2943,16 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, > gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); > } > > -#define GEN_CMP0(NAME, COND) \ > - static void gen_##NAME##0_i32(TCGv_i32 d, TCGv_i32 a) \ > - { \ > - tcg_gen_negsetcond_i32(COND, d, a, tcg_constant_i32(0)); \ > - } \ > - static void gen_##NAME##0_i64(TCGv_i64 d, TCGv_i64 a) \ > - { \ > - tcg_gen_negsetcond_i64(COND, d, a, tcg_constant_i64(0)); \ > - } \ > - static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \ > - { \ > - TCGv_vec zero = tcg_constant_vec_matching(d, vece, 0); \ > - tcg_gen_cmp_vec(COND, vece, d, a, zero); \ > - } \ > - void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \ > - uint32_t opr_sz, uint32_t max_sz) \ > - { \ > - const GVecGen2 op[4] = { \ > - { .fno = gen_helper_gvec_##NAME##0_b, \ > - .fniv = gen_##NAME##0_vec, \ > - .opt_opc = vecop_list_cmp, \ > - .vece = MO_8 }, \ > - { .fno = gen_helper_gvec_##NAME##0_h, \ > - .fniv = gen_##NAME##0_vec, \ > - .opt_opc = vecop_list_cmp, \ > - .vece = MO_16 }, \ > - { .fni4 = gen_##NAME##0_i32, \ > - .fniv = gen_##NAME##0_vec, \ > - .opt_opc = vecop_list_cmp, \ > - .vece = MO_32 }, \ > - { .fni8 = gen_##NAME##0_i64, \ > - .fniv = gen_##NAME##0_vec, \ > - .opt_opc = vecop_list_cmp, \ > - .prefer_i64 = TCG_TARGET_REG_BITS == 64, \ > - .vece = MO_64 }, \ > - }; \ > - tcg_gen_gvec_2(d, m, opr_sz, max_sz, &op[vece]); \ > - } > +#define GEN_CMP0(NAME, COND) \ > + void NAME(unsigned vece, uint32_t d, uint32_t m, \ > + uint32_t opr_sz, uint32_t max_sz) \ > + { tcg_gen_gvec_cmpi(COND, vece, d, m, 0, opr_sz, max_sz); } > > -static const TCGOpcode vecop_list_cmp[] = { > - INDEX_op_cmp_vec, 0 > -}; > - > -GEN_CMP0(ceq, TCG_COND_EQ) > -GEN_CMP0(cle, TCG_COND_LE) > -GEN_CMP0(cge, TCG_COND_GE) > -GEN_CMP0(clt, TCG_COND_LT) > -GEN_CMP0(cgt, TCG_COND_GT) > +GEN_CMP0(gen_gvec_ceq0, TCG_COND_EQ) > +GEN_CMP0(gen_gvec_cle0, TCG_COND_LE) > +GEN_CMP0(gen_gvec_cge0, TCG_COND_GE) > +GEN_CMP0(gen_gvec_clt0, TCG_COND_LT) > +GEN_CMP0(gen_gvec_cgt0, TCG_COND_GT) > > #undef GEN_CMP0 > >
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 38ad8dd4bd..89a7392ed3 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -2943,54 +2943,16 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); } -#define GEN_CMP0(NAME, COND) \ - static void gen_##NAME##0_i32(TCGv_i32 d, TCGv_i32 a) \ - { \ - tcg_gen_negsetcond_i32(COND, d, a, tcg_constant_i32(0)); \ - } \ - static void gen_##NAME##0_i64(TCGv_i64 d, TCGv_i64 a) \ - { \ - tcg_gen_negsetcond_i64(COND, d, a, tcg_constant_i64(0)); \ - } \ - static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \ - { \ - TCGv_vec zero = tcg_constant_vec_matching(d, vece, 0); \ - tcg_gen_cmp_vec(COND, vece, d, a, zero); \ - } \ - void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \ - uint32_t opr_sz, uint32_t max_sz) \ - { \ - const GVecGen2 op[4] = { \ - { .fno = gen_helper_gvec_##NAME##0_b, \ - .fniv = gen_##NAME##0_vec, \ - .opt_opc = vecop_list_cmp, \ - .vece = MO_8 }, \ - { .fno = gen_helper_gvec_##NAME##0_h, \ - .fniv = gen_##NAME##0_vec, \ - .opt_opc = vecop_list_cmp, \ - .vece = MO_16 }, \ - { .fni4 = gen_##NAME##0_i32, \ - .fniv = gen_##NAME##0_vec, \ - .opt_opc = vecop_list_cmp, \ - .vece = MO_32 }, \ - { .fni8 = gen_##NAME##0_i64, \ - .fniv = gen_##NAME##0_vec, \ - .opt_opc = vecop_list_cmp, \ - .prefer_i64 = TCG_TARGET_REG_BITS == 64, \ - .vece = MO_64 }, \ - }; \ - tcg_gen_gvec_2(d, m, opr_sz, max_sz, &op[vece]); \ - } +#define GEN_CMP0(NAME, COND) \ + void NAME(unsigned vece, uint32_t d, uint32_t m, \ + uint32_t opr_sz, uint32_t max_sz) \ + { tcg_gen_gvec_cmpi(COND, vece, d, m, 0, opr_sz, max_sz); } -static const TCGOpcode vecop_list_cmp[] = { - INDEX_op_cmp_vec, 0 -}; - -GEN_CMP0(ceq, TCG_COND_EQ) -GEN_CMP0(cle, TCG_COND_LE) -GEN_CMP0(cge, TCG_COND_GE) -GEN_CMP0(clt, TCG_COND_LT) -GEN_CMP0(cgt, TCG_COND_GT) +GEN_CMP0(gen_gvec_ceq0, TCG_COND_EQ) +GEN_CMP0(gen_gvec_cle0, TCG_COND_LE) +GEN_CMP0(gen_gvec_cge0, TCG_COND_GE) +GEN_CMP0(gen_gvec_clt0, TCG_COND_LT) +GEN_CMP0(gen_gvec_cgt0, TCG_COND_GT) #undef GEN_CMP0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/translate.c | 56 ++++++-------------------------------- 1 file changed, 9 insertions(+), 47 deletions(-)