| Message ID | 558c6b70090ea7220bfb0b6e7d81828025018376.1693996662.git.quic_varada@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable cpufreq for IPQ5332 & IPQ9574 | expand |
On Thu, 7 Sept 2023 at 08:23, Varadarajan Narayanan <quic_varada@quicinc.com> wrote: > > IPQ53xx have different OPPs available for the CPU based on > SoC variant. This can be determined through use of an eFuse > register present in the silicon. > > Added support for ipq53xx on nvmem driver which helps to > determine OPPs at runtime based on the eFuse register which > has the CPU frequency limits. opp-supported-hw dt binding > can be used to indicate the available OPPs for each limit. > > nvmem driver also creates the "cpufreq-dt" platform_device after > passing the version matching data to the OPP framework so that the > cpufreq-dt handles the actual cpufreq implementation. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > drivers/cpufreq/cpufreq-dt-platdev.c | 1 + > drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++++++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c > index 02ec58a..f0c45d4 100644 > --- a/drivers/cpufreq/cpufreq-dt-platdev.c > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c > @@ -178,6 +178,7 @@ static const struct of_device_id blocklist[] __initconst = { > { .compatible = "ti,am625", }, > { .compatible = "ti,am62a7", }, > > + { .compatible = "qcom,ipq5332", }, > { .compatible = "qcom,ipq8064", }, > { .compatible = "qcom,apq8064", }, > { .compatible = "qcom,msm8974", }, > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c > index 84d7033..49d21b0 100644 > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c > @@ -146,6 +146,20 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, > return PTR_ERR(speedbin); > > switch (msm_id) { > + case QCOM_ID_IPQ5332: > + case QCOM_ID_IPQ5322: > + case QCOM_ID_IPQ5312: > + case QCOM_ID_IPQ5302: > + case QCOM_ID_IPQ5300: msm8996 was bad enough. Can we use compat strings instead? Or make this a default for qcom_cpufreq_kryo_name_version()? > + /* Fuse Value Freq BIT to set > + * --------------------------------- > + * 2’b00 No Limit BIT(0) > + * 2’b01 1.5 GHz BIT(1) > + * 2’b10 1.2 Ghz BIT(2) > + * 2’b11 1.0 GHz BIT(3) > + */ > + drv->versions = 1 << (unsigned int)(*speedbin); > + break; > case QCOM_ID_MSM8996: > case QCOM_ID_APQ8096: > drv->versions = 1 << (unsigned int)(*speedbin); > @@ -359,6 +373,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { > { .compatible = "qcom,apq8096", .data = &match_data_kryo }, > { .compatible = "qcom,msm8996", .data = &match_data_kryo }, > { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, > + { .compatible = "qcom,ipq5332", .data = &match_data_kryo }, > { .compatible = "qcom,ipq8064", .data = &match_data_krait }, > { .compatible = "qcom,apq8064", .data = &match_data_krait }, > { .compatible = "qcom,msm8974", .data = &match_data_krait }, > -- > 2.7.4 >
On 07/09/2023 06:21, Varadarajan Narayanan wrote: > IPQ53xx have different OPPs available for the CPU based on > SoC variant. This can be determined through use of an eFuse > register present in the silicon. > > Added support for ipq53xx on nvmem driver which helps to > determine OPPs at runtime based on the eFuse register which > has the CPU frequency limits. opp-supported-hw dt binding > can be used to indicate the available OPPs for each limit. > > nvmem driver also creates the "cpufreq-dt" platform_device after > passing the version matching data to the OPP framework so that the > cpufreq-dt handles the actual cpufreq implementation. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > drivers/cpufreq/cpufreq-dt-platdev.c | 1 + > drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++++++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c > index 02ec58a..f0c45d4 100644 > --- a/drivers/cpufreq/cpufreq-dt-platdev.c > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c > @@ -178,6 +178,7 @@ static const struct of_device_id blocklist[] __initconst = { > { .compatible = "ti,am625", }, > { .compatible = "ti,am62a7", }, > > + { .compatible = "qcom,ipq5332", }, > { .compatible = "qcom,ipq8064", }, > { .compatible = "qcom,apq8064", }, > { .compatible = "qcom,msm8974", }, > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c > index 84d7033..49d21b0 100644 > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c > @@ -146,6 +146,20 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, > return PTR_ERR(speedbin); > > switch (msm_id) { > + case QCOM_ID_IPQ5332: > + case QCOM_ID_IPQ5322: > + case QCOM_ID_IPQ5312: > + case QCOM_ID_IPQ5302: > + case QCOM_ID_IPQ5300: > + /* Fuse Value Freq BIT to set > + * --------------------------------- > + * 2’b00 No Limit BIT(0) > + * 2’b01 1.5 GHz BIT(1) > + * 2’b10 1.2 Ghz BIT(2) > + * 2’b11 1.0 GHz BIT(3) > + */ > + drv->versions = 1 << (unsigned int)(*speedbin); > + break; I like that you've included a comment however, the switch is an ordered list and these values should come after QCOM_ID_APQ8096SG #define QCOM_ID_MSM8996 246 #define QCOM_ID_APQ8096 291 #define QCOM_ID_MSM8996SG 305 #define QCOM_ID_APQ8096SG 312 #define QCOM_ID_IPQ5332 592 ... #define QCOM_ID_IPQ5300 624 > case QCOM_ID_MSM8996: > case QCOM_ID_APQ8096: > drv->versions = 1 << (unsigned int)(*speedbin); > @@ -359,6 +373,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { > { .compatible = "qcom,apq8096", .data = &match_data_kryo }, > { .compatible = "qcom,msm8996", .data = &match_data_kryo }, > { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, > + { .compatible = "qcom,ipq5332", .data = &match_data_kryo }, > { .compatible = "qcom,ipq8064", .data = &match_data_krait }, > { .compatible = "qcom,apq8064", .data = &match_data_krait }, > { .compatible = "qcom,msm8974", .data = &match_data_krait }, Other than that. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- bod
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 02ec58a..f0c45d4 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -178,6 +178,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "ti,am625", }, { .compatible = "ti,am62a7", }, + { .compatible = "qcom,ipq5332", }, { .compatible = "qcom,ipq8064", }, { .compatible = "qcom,apq8064", }, { .compatible = "qcom,msm8974", }, diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 84d7033..49d21b0 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -146,6 +146,20 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, return PTR_ERR(speedbin); switch (msm_id) { + case QCOM_ID_IPQ5332: + case QCOM_ID_IPQ5322: + case QCOM_ID_IPQ5312: + case QCOM_ID_IPQ5302: + case QCOM_ID_IPQ5300: + /* Fuse Value Freq BIT to set + * --------------------------------- + * 2’b00 No Limit BIT(0) + * 2’b01 1.5 GHz BIT(1) + * 2’b10 1.2 Ghz BIT(2) + * 2’b11 1.0 GHz BIT(3) + */ + drv->versions = 1 << (unsigned int)(*speedbin); + break; case QCOM_ID_MSM8996: case QCOM_ID_APQ8096: drv->versions = 1 << (unsigned int)(*speedbin); @@ -359,6 +373,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,apq8096", .data = &match_data_kryo }, { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, + { .compatible = "qcom,ipq5332", .data = &match_data_kryo }, { .compatible = "qcom,ipq8064", .data = &match_data_krait }, { .compatible = "qcom,apq8064", .data = &match_data_krait }, { .compatible = "qcom,msm8974", .data = &match_data_krait },