diff mbox series

target/mips: Fix MSA BZ/BNZ opcodes displacement

Message ID 20230914085807.12241-1-philmd@linaro.org
State Superseded
Headers show
Series target/mips: Fix MSA BZ/BNZ opcodes displacement | expand

Commit Message

Philippe Mathieu-Daudé Sept. 14, 2023, 8:58 a.m. UTC
The PC offset is *signed*.

Cc: qemu-stable@nongnu.org
Reported-by: Sergey Evlashev <vectorchiefrocks@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624
Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/msa.decode | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Richard Henderson Sept. 14, 2023, 1:20 p.m. UTC | #1
On 9/14/23 01:58, Philippe Mathieu-Daudé wrote:
> The PC offset is*signed*.
> 
> Cc:qemu-stable@nongnu.org
> Reported-by: Sergey Evlashev<vectorchiefrocks@gmail.com>
> Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1624
> Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE")
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   target/mips/tcg/msa.decode | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 9575289195..4410e2a02e 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -31,8 +31,8 @@ 
 
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
 @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_i
-@bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
-@bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
+@bz_v               ...... ... ..    wt:5 sa:s16            &msa_bz df=3
+@bz                 ...... ...  df:2 wt:5 sa:s16            &msa_bz
 @elm_df             ...... .... ......    ws:5 wd:5 ......  &msa_elm_df df=%elm_df n=%elm_n
 @elm                ...... ..........     ws:5 wd:5 ......  &msa_elm
 @vec                ...... .....     wt:5 ws:5 wd:5 ......  &msa_r df=0