diff mbox series

[08/13] clk: divider: stop early if an optimal divider is found

Message ID 20230918-imx8mp-dtsi-v1-8-1d008b3237c0@skidata.com
State New
Headers show
Series imx8mp: first clock propagation attempt (for LVDS) | expand

Commit Message

Benjamin Bara Sept. 17, 2023, 10:40 p.m. UTC 
From: Benjamin Bara <benjamin.bara@skidata.com>

During finding the best divider, the current implementation asks the
parent for the best rate for all its available dividers. If there are a
lot of supported divider values and the maximum divider is far from the
target rate, this can lead to many iterations. Depending on the parent,
the process of calculating the best fitting rate can be quite complex.

Therefore, return early if an optimal divider has been found.

Signed-off-by: Benjamin Bara <benjamin.bara@skidata.com>
---
 drivers/clk/clk-divider.c | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index a2c2b5203b0a..61b40dfb4e6f 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -332,6 +332,15 @@  static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
 			bestdiv = i;
 			best = now;
 			*best_parent_rate = parent_rate;
+			if (now == rate)
+				/*
+				 * Calculating fitting PLL parameters, which
+				 * might be done in parent's round_rate, can be
+				 * time-consuming. Therefore, the lowest parent
+				 * rate which gives us the exact required rate
+				 * is already optimal.
+				 */
+				return i;
 		}
 	}