| Message ID | 20230929142852.578394-4-gatien.chevallier@foss.st.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Introduce STM32 Firewall framework | expand |
On Fri, 29 Sep 2023 16:28:44 +0200, Gatien Chevallier wrote: > Document RIFSC (RIF security controller). RIFSC is a firewall controller > composed of different kinds of hardware resources. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> > --- > > Changes in V5: > - Renamed feature-domain* to access-control* > > Changes in V2: > - Corrected errors highlighted by Rob's robot > - No longer define the maxItems for the "feature-domains" > property > - Fix example (node name, status) > - Declare "feature-domain-names" as an optional > property for child nodes > - Fix description of "feature-domains" property > > .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml: access-controller: missing type definition /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml: access-control-provider: missing type definition /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.example.dtb: serial@400e0000: Unevaluated properties are not allowed ('access-controller' was unexpected) from schema $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230929142852.578394-4-gatien.chevallier@foss.st.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Fri, Sep 29, 2023 at 04:28:44PM +0200, Gatien Chevallier wrote: > Document RIFSC (RIF security controller). RIFSC is a firewall controller > composed of different kinds of hardware resources. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> > --- > > Changes in V5: > - Renamed feature-domain* to access-control* > > Changes in V2: > - Corrected errors highlighted by Rob's robot > - No longer define the maxItems for the "feature-domains" > property > - Fix example (node name, status) > - Declare "feature-domain-names" as an optional > property for child nodes > - Fix description of "feature-domains" property > > .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > > diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > new file mode 100644 > index 000000000000..c28fceff3036 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STM32 Resource isolation framework security controller > + > +maintainers: > + - Gatien Chevallier <gatien.chevallier@foss.st.com> > + > +description: | > + Resource isolation framework (RIF) is a comprehensive set of hardware blocks > + designed to enforce and manage isolation of STM32 hardware resources like > + memory and peripherals. > + > + The RIFSC (RIF security controller) is composed of three sets of registers, > + each managing a specific set of hardware resources: > + - RISC registers associated with RISUP logic (resource isolation device unit > + for peripherals), assign all non-RIF aware peripherals to zero, one or > + any security domains (secure, privilege, compartment). > + - RIMC registers: associated with RIMU logic (resource isolation master > + unit), assign all non RIF-aware bus master to one security domain by > + setting secure, privileged and compartment information on the system bus. > + Alternatively, the RISUP logic controlling the device port access to a > + peripheral can assign target bus attributes to this peripheral master port > + (supported attribute: CID). > + - RISC registers associated with RISAL logic (resource isolation device unit > + for address space - Lite version), assign address space subregions to one > + security domains (secure, privilege, compartment). > + > +properties: > + compatible: > + contains: > + const: st,stm32mp25-rifsc > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 > + > + ranges: true > + > + "#access-controller-cells": > + const: 1 You should define what the cells contain here. > + > + access-control-provider: true > + > +patternProperties: > + "^.*@[0-9a-f]+$": > + description: Peripherals > + type: object additionalProperties: true > + properties: > + access-controller: > + minItems: 1 > + description: > + The phandle of the firewall controller of the peripheral and the > + platform-specific firewall ID of the peripheral. > + > + access-controller-names: > + minItems: 1 Drop all this. You have to define these in the specific device schemas anyways. > + > + required: > + - access-controller > + > +required: > + - compatible > + - reg > + - "#address-cells" > + - "#size-cells" > + - access-control-provider > + - "#access-controller-cells" > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + // In this example, the usart2 device refers to rifsc as its domain > + // controller. > + // Access rights are verified before creating devices. > + > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + rifsc: bus@42080000 { > + compatible = "st,stm32mp25-rifsc"; > + reg = <0x42080000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + access-control-provider; > + #access-controller-cells = <1>; > + ranges; > + > + usart2: serial@400e0000 { > + compatible = "st,stm32h7-uart"; > + reg = <0x400e0000 0x400>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ck_flexgen_08>; > + access-controller = <&rifsc 32>; > + }; > + }; > -- > 2.25.1 >
On 10/2/23 20:30, Rob Herring wrote: > On Fri, Sep 29, 2023 at 04:28:44PM +0200, Gatien Chevallier wrote: >> Document RIFSC (RIF security controller). RIFSC is a firewall controller >> composed of different kinds of hardware resources. >> >> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> >> --- >> >> Changes in V5: >> - Renamed feature-domain* to access-control* >> >> Changes in V2: >> - Corrected errors highlighted by Rob's robot >> - No longer define the maxItems for the "feature-domains" >> property >> - Fix example (node name, status) >> - Declare "feature-domain-names" as an optional >> property for child nodes >> - Fix description of "feature-domains" property >> >> .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ >> 1 file changed, 105 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml >> >> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml >> new file mode 100644 >> index 000000000000..c28fceff3036 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml >> @@ -0,0 +1,105 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: STM32 Resource isolation framework security controller >> + >> +maintainers: >> + - Gatien Chevallier <gatien.chevallier@foss.st.com> >> + >> +description: | >> + Resource isolation framework (RIF) is a comprehensive set of hardware blocks >> + designed to enforce and manage isolation of STM32 hardware resources like >> + memory and peripherals. >> + >> + The RIFSC (RIF security controller) is composed of three sets of registers, >> + each managing a specific set of hardware resources: >> + - RISC registers associated with RISUP logic (resource isolation device unit >> + for peripherals), assign all non-RIF aware peripherals to zero, one or >> + any security domains (secure, privilege, compartment). >> + - RIMC registers: associated with RIMU logic (resource isolation master >> + unit), assign all non RIF-aware bus master to one security domain by >> + setting secure, privileged and compartment information on the system bus. >> + Alternatively, the RISUP logic controlling the device port access to a >> + peripheral can assign target bus attributes to this peripheral master port >> + (supported attribute: CID). >> + - RISC registers associated with RISAL logic (resource isolation device unit >> + for address space - Lite version), assign address space subregions to one >> + security domains (secure, privilege, compartment). >> + >> +properties: >> + compatible: >> + contains: >> + const: st,stm32mp25-rifsc >> + >> + reg: >> + maxItems: 1 >> + >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 1 >> + >> + ranges: true >> + >> + "#access-controller-cells": >> + const: 1 > > You should define what the cells contain here. > Ok, I'll do this as well for the ETZPC binding >> + >> + access-control-provider: true >> + Will be dropped, ditto for ETZPC. >> +patternProperties: >> + "^.*@[0-9a-f]+$": >> + description: Peripherals >> + type: object > > additionalProperties: true > >> + properties: >> + access-controller: >> + minItems: 1 >> + description: >> + The phandle of the firewall controller of the peripheral and the >> + platform-specific firewall ID of the peripheral. >> + >> + access-controller-names: >> + minItems: 1 > > Drop all this. You have to define these in the specific device schemas > anyways. > I guess that: patternProperties: "^.*@[0-9a-f]+$": description: Peripherals type: object required: - access-controller is sufficient if I describe what the content of the cells will be in the "#access-controller-cells" above. It avoids redundant information. I'll make the change for V6, thank you. Best regards, Gatien >> + >> + required: >> + - access-controller >> + >> +required: >> + - compatible >> + - reg >> + - "#address-cells" >> + - "#size-cells" >> + - access-control-provider >> + - "#access-controller-cells" >> + - ranges >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + // In this example, the usart2 device refers to rifsc as its domain >> + // controller. >> + // Access rights are verified before creating devices. >> + >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + rifsc: bus@42080000 { >> + compatible = "st,stm32mp25-rifsc"; >> + reg = <0x42080000 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + access-control-provider; >> + #access-controller-cells = <1>; >> + ranges; >> + >> + usart2: serial@400e0000 { >> + compatible = "st,stm32h7-uart"; >> + reg = <0x400e0000 0x400>; >> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ck_flexgen_08>; >> + access-controller = <&rifsc 32>; >> + }; >> + }; >> -- >> 2.25.1 >>
diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml new file mode 100644 index 000000000000..c28fceff3036 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation framework security controller + +maintainers: + - Gatien Chevallier <gatien.chevallier@foss.st.com> + +description: | + Resource isolation framework (RIF) is a comprehensive set of hardware blocks + designed to enforce and manage isolation of STM32 hardware resources like + memory and peripherals. + + The RIFSC (RIF security controller) is composed of three sets of registers, + each managing a specific set of hardware resources: + - RISC registers associated with RISUP logic (resource isolation device unit + for peripherals), assign all non-RIF aware peripherals to zero, one or + any security domains (secure, privilege, compartment). + - RIMC registers: associated with RIMU logic (resource isolation master + unit), assign all non RIF-aware bus master to one security domain by + setting secure, privileged and compartment information on the system bus. + Alternatively, the RISUP logic controlling the device port access to a + peripheral can assign target bus attributes to this peripheral master port + (supported attribute: CID). + - RISC registers associated with RISAL logic (resource isolation device unit + for address space - Lite version), assign address space subregions to one + security domains (secure, privilege, compartment). + +properties: + compatible: + contains: + const: st,stm32mp25-rifsc + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + + access-control-provider: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + properties: + access-controller: + minItems: 1 + description: + The phandle of the firewall controller of the peripheral and the + platform-specific firewall ID of the peripheral. + + access-controller-names: + minItems: 1 + + required: + - access-controller + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - access-control-provider + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include <dt-bindings/interrupt-controller/arm-gic.h> + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + access-control-provider; + #access-controller-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + access-controller = <&rifsc 32>; + }; + };
Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> --- Changes in V5: - Renamed feature-domain* to access-control* Changes in V2: - Corrected errors highlighted by Rob's robot - No longer define the maxItems for the "feature-domains" property - Fix example (node name, status) - Declare "feature-domain-names" as an optional property for child nodes - Fix description of "feature-domains" property .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml