diff mbox series

[1/2] arm64: dts: socfpga: agilex/stratix10: move base_fpga_region out of soc node

Message ID 20230929103600.262856-1-dinguyen@kernel.org
State New
Headers show
Series [1/2] arm64: dts: socfpga: agilex/stratix10: move base_fpga_region out of soc node | expand

Commit Message

Dinh Nguyen Sept. 29, 2023, 10:35 a.m. UTC 
The soc node is supposed to only have device nodes with MMIO addresses,
thus move the base_fpga_region outside of the soc node.

soc: base_fpga_region: {'#address-cells': [[2]], '#size-cells': [[2]],
'compatible': ['fpga-region'], 'fpga-mgr': [[6]]} should not be valid
under {'type': 'object'}

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 14 +++++++-------
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi     | 14 +++++++-------
 2 files changed, 14 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 439497ab967d..4ad4cee83370 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -125,6 +125,13 @@  qspi_clk: qspi-clk {
 		};
 	};
 
+	base_fpga_region {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "fpga-region";
+		fpga-mgr = <&fpga_mgr>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -133,13 +140,6 @@  soc {
 		interrupt-parent = <&intc>;
 		ranges = <0 0 0 0xffffffff>;
 
-		base_fpga_region {
-			#address-cells = <0x2>;
-			#size-cells = <0x2>;
-			compatible = "fpga-region";
-			fpga-mgr = <&fpga_mgr>;
-		};
-
 		clkmgr: clock-controller@ffd10000 {
 			compatible = "intel,stratix10-clkmgr";
 			reg = <0xffd10000 0x1000>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index d3adb6a130ae..109bd4c35c3b 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -130,6 +130,13 @@  usbphy0: usbphy {
 		compatible = "usb-nop-xceiv";
 	};
 
+	base_fpga_region {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "fpga-region";
+		fpga-mgr = <&fpga_mgr>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -138,13 +145,6 @@  soc {
 		interrupt-parent = <&intc>;
 		ranges = <0 0 0 0xffffffff>;
 
-		base_fpga_region {
-			#address-cells = <0x2>;
-			#size-cells = <0x2>;
-			compatible = "fpga-region";
-			fpga-mgr = <&fpga_mgr>;
-		};
-
 		clkmgr: clock-controller@ffd10000 {
 			compatible = "intel,agilex-clkmgr";
 			reg = <0xffd10000 0x1000>;