@@ -767,6 +767,29 @@ static enum pci_bus_speed agp_speed(int agp3, int agpstat)
return agp_speeds[index];
}
+/*
+ * Implementation Note in PCIe r6.0.1 sec 7.5.3.18 recommends determining
+ * supported link speeds using the Supported Link Speeds Vector in the Link
+ * Capabilities 2 Register (when available).
+ */
+static u8 pcie_get_supported_speeds(u32 linkcap, u32 linkcap2)
+{
+ u8 speeds;
+
+ speeds = linkcap2 & PCI_EXP_LNKCAP2_SLS;
+ if (speeds)
+ return speeds;
+
+ /*
+ * Synthetize supported link speeds from the Max Link Speed in the
+ * Link Capabilities Register.
+ */
+ speeds = PCI_EXP_LNKCAP2_SLS_2_5GB;
+ if ((linkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
+ speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB;
+ return speeds;
+}
+
static void pci_set_bus_speed(struct pci_bus *bus)
{
struct pci_dev *bridge = bus->self;
@@ -814,12 +837,15 @@ static void pci_set_bus_speed(struct pci_bus *bus)
}
if (pci_is_pcie(bridge)) {
- u32 linkcap;
+ u32 linkcap, linkcap2;
u16 linksta;
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
+ pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP2, &linkcap2);
+ bus->pcie_bus_speeds = pcie_get_supported_speeds(linkcap, linkcap2);
+
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
pcie_update_link_speed(bus, linksta);
}
@@ -664,6 +664,7 @@ struct pci_bus {
unsigned char primary; /* Number of primary bridge */
unsigned char max_bus_speed; /* enum pci_bus_speed */
unsigned char cur_bus_speed; /* enum pci_bus_speed */
+ u8 pcie_bus_speeds;/* Supported Link Speeds Vector (+ reserved 0 at LSB) */
#ifdef CONFIG_PCI_DOMAINS_GENERIC
int domain_nr;
#endif
@@ -674,6 +674,7 @@
#define PCI_EXP_DEVSTA2 0x2a /* Device Status 2 */
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 0x2c /* end of v2 EPs w/o link */
#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities 2 */
+#define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
struct pci_bus stores max_bus_speed. Implementation Note in PCIe r6.0.1 sec 7.5.3.18, however, recommends determining supported Link Speeds using the Supported Link Speeds Vector in the Link Capabilities 2 Register (when available). Add pcie_bus_speeds into struct pci_bus which caches the Supported Link Speeds. The value is taken directly from the Supported Link Speeds Vector or synthetized from the Max Link Speed in the Link Capabilities Register when the Link Capabilities 2 Register is not available. pcie_bus_speeds field keeps the extra reserved zero at the least significant bit to match the Link Capabilities 2 Register layouting. Suggested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> --- drivers/pci/probe.c | 28 +++++++++++++++++++++++++++- include/linux/pci.h | 1 + include/uapi/linux/pci_regs.h | 1 + 3 files changed, 29 insertions(+), 1 deletion(-)