| Message ID | 20231003120846.28626-3-quic_nsekar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable IPQ5018 PCI support | expand |
On 03/10/2023 14:08, Nitheesh Sekar wrote: > Add support for the PCIe controller on the Qualcomm > IPQ5108 SoC to the bindings. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, you can skip it (please do not feel offended by me posting it here - no bad intentions intended). If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions, under or above your Signed-off-by tag. Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply. https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577 Best regards, Krzysztof
On 3.10.2023 14:08, Nitheesh Sekar wrote: > Add support for the PCIe controller on the Qualcomm > IPQ5108 SoC to the bindings. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > --- [...] > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-ipq5018 > + then: > + properties: > + clocks: > + minItems: 6 > + maxItems: 6 > + clock-names: > + items: > + - const: iface # PCIe to SysNOC BIU clock What's a BIU? Konrad
On 10/7/2023 5:55 AM, Konrad Dybcio wrote: > On 3.10.2023 14:08, Nitheesh Sekar wrote: >> Add support for the PCIe controller on the Qualcomm >> IPQ5108 SoC to the bindings. >> >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >> --- > [...] > >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,pcie-ipq5018 >> + then: >> + properties: >> + clocks: >> + minItems: 6 >> + maxItems: 6 >> + clock-names: >> + items: >> + - const: iface # PCIe to SysNOC BIU clock > What's a BIU? > > Konrad It is Bus Interface Unit. Thanks, Nitheesh
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index eadba38171e1..72e24094ec7e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -170,6 +171,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 then: @@ -332,6 +334,39 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5018 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_bridge # AXI bridge clock + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core sticky reset + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_s_sticky # AXI slave sticky reset + - if: properties: compatible: @@ -790,6 +825,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074
Add support for the PCIe controller on the Qualcomm IPQ5108 SoC to the bindings. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+)