| Message ID | 20231003120846.28626-2-quic_nsekar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable IPQ5018 PCI support | expand |
On 10/4/2023 12:27 PM, Krzysztof Kozlowski wrote: > On 03/10/2023 14:08, Nitheesh Sekar wrote: >> Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018. >> >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Thank you for your patch. There is something to discuss/improve. Sure. Will learn and improve. > > >> --- >> .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 77 +++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml >> new file mode 100644 >> index 000000000000..6b2574f9532e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml > Filename should match compatibles and they do not use 28lp. Sure. will remove the 28lp. added it based on the file name. Is "qcom,uniphy-pcie.yaml" good ? Because this will be used for other SoCs as well which will have different compatibles. So i did not include the SoC name, lane and speed info which i have used int he compatible names. > >> @@ -0,0 +1,77 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/qcom,uniphy-pcie-28lp.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm UNIPHY PCIe 28LP PHY driver > Driver as Linux driver? Drop. Describe the hardware instead. > >> + >> +maintainers: >> + - Nitheesh Sekar <quic_nsekar@quicinc.com> >> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,ipq5018-uniphy-pcie-gen2x1 >> + - qcom,ipq5018-uniphy-pcie-gen2x2 >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: pipe_clk > Drop _clk... or even drop entire clock-names. Not needed for one entry. Sure. Will drop "_clk" part. > >> + >> + resets: >> + maxItems: 2 >> + >> + reset-names: >> + items: >> + - const: phy >> + - const: phy_phy > These are absolutely terrible names. If you have third one, it would be > "phy_phy_phy"? Drop or provide something useful. Sure. Will update. Thanks, Nitheesh
diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml new file mode 100644 index 000000000000..6b2574f9532e --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,uniphy-pcie-28lp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY driver + +maintainers: + - Nitheesh Sekar <quic_nsekar@quicinc.com> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> + +properties: + compatible: + enum: + - qcom,ipq5018-uniphy-pcie-gen2x1 + - qcom,ipq5018-uniphy-pcie-gen2x2 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pipe_clk + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: phy_phy + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - resets + - reset-names + - clocks + - clock-names + - "#phy-cells" + - "#clock-cells" + - clock-output-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq5018.h> + #include <dt-bindings/reset/qcom,gcc-ipq5018.h> + + phy@86000 { + compatible = "qcom,ipq5018-uniphy-pcie-gen2x2"; + reg = <0x86000 0x800>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe_clk"; + clock-output-names = "pcie0_pipe_clk"; + assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>; + assigned-clock-rates = <125000000>; + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", "phy_phy"; + };
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> --- .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml