@@ -5403,149 +5403,6 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e)
TRANS(FCMPq, ALL, do_fcmpq, a, false)
TRANS(FCMPEq, ALL, do_fcmpq, a, true)
-#define CHECK_IU_FEATURE(dc, FEATURE) \
- if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
- goto illegal_insn;
-#define CHECK_FPU_FEATURE(dc, FEATURE) \
- if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
- goto nfpu_insn;
-
-/* before an instruction, dc->pc must be static */
-static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
-{
- unsigned int opc = GET_FIELD(insn, 0, 1);
-
- switch (opc) {
- case 0:
- goto illegal_insn; /* in decodetree */
- case 1:
- g_assert_not_reached(); /* in decodetree */
- case 2: /* FPU & Logical Operations */
- {
- unsigned int xop = GET_FIELD(insn, 7, 12);
-
- if (xop == 0x34) { /* FPU Operations */
- goto illegal_insn; /* in decodetree */
- } else if (xop == 0x35) { /* FPU Operations */
- goto illegal_insn; /* in decodetree */
- } else if (xop == 0x36) {
-#ifdef TARGET_SPARC64
- /* VIS */
- int opf = GET_FIELD_SP(insn, 5, 13);
-
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
-
- switch (opf) {
- case 0x000: /* VIS I edge8cc */
- case 0x001: /* VIS II edge8n */
- case 0x002: /* VIS I edge8lcc */
- case 0x003: /* VIS II edge8ln */
- case 0x004: /* VIS I edge16cc */
- case 0x005: /* VIS II edge16n */
- case 0x006: /* VIS I edge16lcc */
- case 0x007: /* VIS II edge16ln */
- case 0x008: /* VIS I edge32cc */
- case 0x009: /* VIS II edge32n */
- case 0x00a: /* VIS I edge32lcc */
- case 0x00b: /* VIS II edge32ln */
- case 0x010: /* VIS I array8 */
- case 0x012: /* VIS I array16 */
- case 0x014: /* VIS I array32 */
- case 0x018: /* VIS I alignaddr */
- case 0x01a: /* VIS I alignaddrl */
- case 0x019: /* VIS II bmask */
- case 0x067: /* VIS I fnot2s */
- case 0x06b: /* VIS I fnot1s */
- case 0x075: /* VIS I fsrc1s */
- case 0x079: /* VIS I fsrc2s */
- case 0x066: /* VIS I fnot2 */
- case 0x06a: /* VIS I fnot1 */
- case 0x074: /* VIS I fsrc1 */
- case 0x078: /* VIS I fsrc2 */
- case 0x051: /* VIS I fpadd16s */
- case 0x053: /* VIS I fpadd32s */
- case 0x055: /* VIS I fpsub16s */
- case 0x057: /* VIS I fpsub32s */
- case 0x063: /* VIS I fnors */
- case 0x065: /* VIS I fandnot2s */
- case 0x069: /* VIS I fandnot1s */
- case 0x06d: /* VIS I fxors */
- case 0x06f: /* VIS I fnands */
- case 0x071: /* VIS I fands */
- case 0x073: /* VIS I fxnors */
- case 0x077: /* VIS I fornot2s */
- case 0x07b: /* VIS I fornot1s */
- case 0x07d: /* VIS I fors */
- case 0x050: /* VIS I fpadd16 */
- case 0x052: /* VIS I fpadd32 */
- case 0x054: /* VIS I fpsub16 */
- case 0x056: /* VIS I fpsub32 */
- case 0x062: /* VIS I fnor */
- case 0x064: /* VIS I fandnot2 */
- case 0x068: /* VIS I fandnot1 */
- case 0x06c: /* VIS I fxor */
- case 0x06e: /* VIS I fnand */
- case 0x070: /* VIS I fand */
- case 0x072: /* VIS I fxnor */
- case 0x076: /* VIS I fornot2 */
- case 0x07a: /* VIS I fornot1 */
- case 0x07c: /* VIS I for */
- case 0x031: /* VIS I fmul8x16 */
- case 0x033: /* VIS I fmul8x16au */
- case 0x035: /* VIS I fmul8x16al */
- case 0x036: /* VIS I fmul8sux16 */
- case 0x037: /* VIS I fmul8ulx16 */
- case 0x038: /* VIS I fmuld8sux16 */
- case 0x039: /* VIS I fmuld8ulx16 */
- case 0x04b: /* VIS I fpmerge */
- case 0x04d: /* VIS I fexpand */
- case 0x03e: /* VIS I pdist */
- case 0x03a: /* VIS I fpack32 */
- case 0x048: /* VIS I faligndata */
- case 0x04c: /* VIS II bshuffle */
- case 0x020: /* VIS I fcmple16 */
- case 0x022: /* VIS I fcmpne16 */
- case 0x024: /* VIS I fcmple32 */
- case 0x026: /* VIS I fcmpne32 */
- case 0x028: /* VIS I fcmpgt16 */
- case 0x02a: /* VIS I fcmpeq16 */
- case 0x02c: /* VIS I fcmpgt32 */
- case 0x02e: /* VIS I fcmpeq32 */
- case 0x03b: /* VIS I fpack16 */
- case 0x03d: /* VIS I fpackfix */
- case 0x060: /* VIS I fzero */
- case 0x061: /* VIS I fzeros */
- case 0x07e: /* VIS I fone */
- case 0x07f: /* VIS I fones */
- g_assert_not_reached(); /* in decodetree */
- case 0x080: /* VIS I shutdown */
- case 0x081: /* VIS II siam */
- // XXX
- goto illegal_insn;
- default:
- goto illegal_insn;
- }
-#endif
- } else {
- goto illegal_insn; /* in decodetree */
- }
- }
- break;
- case 3: /* load/store instructions */
- goto illegal_insn; /* in decodetree */
- }
- advance_pc(dc);
-#ifdef TARGET_SPARC64
- jmp_insn:
-#endif
- return;
- illegal_insn:
- gen_exception(dc, TT_ILL_INSN);
- return;
-}
-
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
@@ -5613,7 +5470,7 @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
dc->base.pc_next += 4;
if (!decode(dc, insn)) {
- disas_sparc_legacy(dc, insn);
+ gen_exception(dc, TT_ILL_INSN);
}
if (dc->base.is_jmp == DISAS_NORETURN) {
All instructions are now converted. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/translate.c | 145 +-------------------------------------- 1 file changed, 1 insertion(+), 144 deletions(-)