[edk2,3/6] Platforms/Styx: remove unused AmdStyxSecLib

Message ID	1470910101-20322-4-git-send-email-ard.biesheuvel@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; From: Ard Biesheuvel <ard.biesheuvel@linaro.org> To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Thu, 11 Aug 2016 12:08:18 +0200 Message-Id: <1470910101-20322-4-git-send-email-ard.biesheuvel@linaro.org> In-Reply-To: <1470910101-20322-1-git-send-email-ard.biesheuvel@linaro.org> References: <1470910101-20322-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 3/6] Platforms/Styx: remove unused AmdStyxSecLib Precedence: list Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" <edk2-devel-bounces@lists.01.org>

diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 6b9446a1387d..01ad69708237 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -154,7 +154,6 @@ DEFINE DO_KCS = 0 PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf - ArmPlatformSecLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/GicV3.S b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/GicV3.S deleted file mode 100644 index 617a6ff0cff0..000000000000 --- a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/GicV3.S +++ /dev/null @@ -1,73 +0,0 @@ -// -// Copyright (c) 2013-2014, ARM Limited. All rights reserved. -// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//** -// Derived from: -// ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S -// -//** - - -#include <AsmMacroIoLibV8.h> - -// Register definitions used by GCC for GICv3 access. -// These are defined by ARMCC, so keep them in the GCC specific code for now. -#define ICC_SRE_EL2 S3_4_C12_C9_5 -#define ICC_SRE_EL3 S3_6_C12_C12_5 -#define ICC_CTLR_EL1 S3_0_C12_C12_4 -#define ICC_CTLR_EL3 S3_6_C12_C12_4 -#define ICC_PMR_EL1 S3_0_C4_C6_0 - -.text -.align 3 - -GCC_ASM_EXPORT(InitializeGicV3) - -/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */ -ASM_PFX(InitializeGicV3): - // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup - // to allow Linux to use GICv3 if it chooses. - - // In order to setup NS side we need to enable it first. - mrs x0, scr_el3 - orr x0, x0, #1 - msr scr_el3, x0 - - // Enable SRE at EL3 and ICC_SRE_EL2 access - mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE - mrs x1, ICC_SRE_EL3 - orr x1, x1, x0 - msr ICC_SRE_EL3, x1 - isb - - // Enable SRE at EL2 and ICC_SRE_EL1 access.. - mrs x1, ICC_SRE_EL2 - orr x1, x1, x0 - msr ICC_SRE_EL2, x1 - isb - - // Configure CPU interface - msr ICC_CTLR_EL3, xzr - isb - msr ICC_CTLR_EL1, xzr - isb - - // The MemoryMap view and Register view may not be consistent, So Set PMR again. - mov w1, #1 << 7 // allow NS access to GICC_PMR - msr ICC_PMR_EL1, x1 - isb - - // Remove the SCR.NS bit - mrs x0, scr_el3 - bic x0, x0, #1 - msr scr_el3, x0 - ret diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/StyxBoot.S b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/StyxBoot.S deleted file mode 100644 index c9e316366eb6..000000000000 --- a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/StyxBoot.S +++ /dev/null @@ -1,182 +0,0 @@ -// -// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. -// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//** -// Derived from: -// ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/RTSMBoot.S -// -//** - -#include <AsmMacroIoLibV8.h> -#include <Base.h> -#include <Library/ArmPlatformLib.h> -#include <AutoGen.h> - -.text -.align 3 - -GCC_ASM_EXPORT(ArmPlatformSecBootAction) -GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) -GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite) -GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead) - -/** - Call at the beginning of the platform boot up - - This function allows the firmware platform to do extra actions at the early - stage of the platform power up. - - Note: This function must be implemented in assembler as there is no stack set up yet - -**/ -ASM_PFX(ArmPlatformSecBootAction): - /* - * Cortex-A57 Errata - */ - // Enable CPUECTLR.SMPEN for SMP - mrs x13, s3_1_c15_c2_1 // Read CPUECTLR - bfi x13, x1, #6, #1 // Set bit 6; SMPEN: Allow PE to receive IC and TLB operations broadcast from others - msr s3_1_c15_c2_1, x13 - isb - - /* - * NIC400 initialization. - * - * Setting all registers to unsecure. - */ - movz x1, #0xFFFF, LSL #16 - movk x1, #0xFFFF - - // NIC400 Bot VDD - movz x0, #0xE1B0, LSL #16 - movk x0, #0x0008 - str w1, [x0] - movk x0, #0x000C - str w1, [x0] - movk x0, #0x0010 - str w1, [x0] - movk x0, #0x0014 - str w1, [x0] - movk x0, #0x0018 - str w1, [x0] - movk x0, #0x0020 - str w1, [x0] - movk x0, #0x0024 - str w1, [x0] - movk x0, #0x0028 - str w1, [x0] - movk x0, #0x002C - str w1, [x0] - movk x0, #0x0030 - str w1, [x0] - movk x0, #0x0038 - str w1, [x0] - movk x0, #0x001C - str w1, [x0] - - // NIC400 Top VDD - movz x0, #0xE1C0, LSL #16 - movk x0, #0x0010 - str w1, [x0] - movk x0, #0x0014 - str w1, [x0] - movk x0, #0x0018 - str w1, [x0] - - // NIC400 TOP VDDN - movz x0, #0xE1D0, LSL #16 - movk x0, #0x0008 - str w1, [x0] - movk x0, #0x000C - str w1, [x0] - movk x0, #0x0010 - str w1, [x0] - movk x0, #0x0014 - str w1, [x0] - movk x0, #0x0018 - str w1, [x0] - movk x0, #0x0020 - str w1, [x0] - movk x0, #0x0024 - str w1, [x0] - movk x0, #0x002C - str w1, [x0] - movk x0, #0x0030 - str w1, [x0] - -# 0000_1111_0111_1111_0000_0001_0000_0001 (0x0F7F0101): -# |||| |||| |||| |||| |||| |||| |||| |||| -# |||| |||| |||| |||| |||| |||| |||| |||+- 0: CLIENTPD (1) -# |||| |||| |||| |||| |||| |||| |||| ||+-- 1: GFRE (0) -# |||| |||| |||| |||| |||| |||| |||| |+--- 2: GFIE (0) -# |||| |||| |||| |||| |||| |||| |||| +---- 3: Reserved (0) -# |||| |||| |||| |||| |||| |||| |||| -# |||| |||| |||| |||| |||| |||| |||+ ----- 4: GCFGFRE (0) -# |||| |||| |||| |||| |||| |||| ||+- ----- 5: GCFGFIE (0) -# |||| |||| |||| |||| |||| |||| ++-- ----- 6-7: Reserved (0) -# |||| |||| |||| |||| |||| |||| -# |||| |||| |||| |||| |||| |||| ---- ----- 8: STALLD (1) -# |||| |||| |||| |||| |||| ||+- ---- ----- 9: GSE (0) -# |||| |||| |||| |||| |||| |+-- ---- ----- 10: USFCFG (0) -# |||| |||| |||| |||| |||| +--- ---- ----- 11: VMIDPNE (0) -# |||| |||| |||| |||| |||| -# |||| |||| |||| |||| |||+ ---- ---- ----- 12: PTM (0) -# |||| |||| |||| |||| ||+- ---- ---- ----- 13: FB (0) -# |||| |||| |||| |||| ++-- ---- ---- ----- 14-15: BSU (0) -# |||| |||| |||| |||| -# |||| |||| |||| ++++ ---- ---- ---- ----- 16-19: MEMATTR (F) -# |||| |||| |||| -# |||| |||| |||+ ---- ---- ---- ---- ----- 20: MTCFG (1) -# |||| |||| ||+- ---- ---- ---- ---- ----- 21: SMCFCFG (1) -# |||| |||| ++-- ---- ---- ---- ---- ----- 22-23: SHCFG (1) -# |||| |||| -# |||| ||++ ---- ---- ---- ---- ---- ----- 24-25: RACFG (3) -# |||| ++-- ---- ---- ---- ---- ---- ----- 26-27: WACFG (3) -# |||| -# ||++ ---- ---- ---- ---- ---- ---- ----- 28-29: NSCFG (0) -# ++-- ---- ---- ---- ---- ---- ---- ----- 30-31: Reserved (0) - - // Workaround for A0, force the memory attributes - ldr x0, =0xE0200000 // SMMU_SCR0 - ldr w1, =0x0F7F0101 - str w1, [x0, #0] - - ldr x0, =0xE0200400 // SMMU_NSCR0 - ldr w1, =0x0F7F0101 - str w1, [x0, #0] - ret - -/** - Initialize the memory where the initial stacks will reside - - This memory can contain the initial stacks (Secure and Secure Monitor stacks). - In some platform, this region is already initialized and the implementation of this function can - do nothing. This memory can also represent the Secure RAM. - This function is called before the satck has been set up. Its implementation must ensure the stack - pointer is not used (probably required to use assembly language) - -**/ -ASM_PFX(ArmPlatformSecBootMemoryInit): - // The SMC does not need to be initialized for RTSM - ret - -/* Write the flag register used to start Secondary cores */ -ASM_PFX(ArmSecMpCoreSecondariesWrite): - // Write to the CPU Mailbox - ret - -/* Read the flag register used to start Secondary cores */ -ASM_PFX(ArmSecMpCoreSecondariesRead): - // Return the value from the CPU Mailbox - mov x0, #0 - ret - diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf deleted file mode 100644 index 9f0823746378..000000000000 --- a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf +++ /dev/null @@ -1,50 +0,0 @@ -#/* @file -# -# Copyright (c) 2011-2013, ARM Limited. All rights reserved. -# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#*/ -#/** -# Derived from: -# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = AmdStyxSecLib - FILE_GUID = af95afa9-fc3f-47b4-9237-d024305cd2e2 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmPlatformSecLib - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - -[LibraryClasses] - IoLib - ArmLib - SerialPortLib - -[Sources.common] - StyxSec.c - -[Sources.AARCH64] - AArch64/StyxBoot.S | GCC - AArch64/GicV3.S | GCC - -[FixedPcd] - gArmTokenSpaceGuid.PcdFvBaseAddress - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/StyxSec.c b/Platforms/AMD/Styx/Library/AmdStyxSecLib/StyxSec.c deleted file mode 100644 index e5ff4ed3a87e..000000000000 --- a/Platforms/AMD/Styx/Library/AmdStyxSecLib/StyxSec.c +++ /dev/null @@ -1,96 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2014, ARM Limited. All rights reserved. -* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ -/** - Derived from: - ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c - -**/ - -#include <Library/IoLib.h> -#include <Library/ArmGicLib.h> -#include <Library/ArmPlatformLib.h> -#include <Library/DebugLib.h> -#include <Library/PcdLib.h> - -#include <Drivers/PL310L2Cache.h> -#include <Drivers/SP804Timer.h> - - -// Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet -VOID -InitializeGicV3 ( - VOID - ); - -/** - Initialize the Secure peripherals and memory regions - - If Trustzone is supported by your platform then this function makes the required initialization - of the secure peripherals and memory regions. - -**/ -VOID -ArmPlatformSecTrustzoneInit ( - IN UINTN MpId - ) -{ - // No TZPC or TZASC on RTSM to initialize -} - -/** - Initialize controllers that must setup at the early stage - - Some peripherals must be initialized in Secure World. - For example, some L2x0 requires to be initialized in Secure World - -**/ -RETURN_STATUS -ArmPlatformSecInitialize ( - IN UINTN MpId - ) -{ - UINT32 Identification; - - // If it is not the primary core then there is nothing to do - if (!ArmPlatformIsPrimaryCore (MpId)) { - return RETURN_SUCCESS; - } - - // Read the GIC Identification Register - Identification = MmioRead32 (FixedPcdGet64(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIIDR); - - // Check if we are GICv3 - if (ARM_GIC_ICCIIDR_GET_ARCH_VERSION(Identification) >= 0x3) { - InitializeGicV3 (); - } - - return RETURN_SUCCESS; -} - -/** - Call before jumping to Normal World - - This function allows the firmware platform to do extra actions before - jumping to the Normal World - -**/ -VOID -ArmPlatformSecExtraAction ( - IN UINTN MpId, - OUT UINTN* JumpAddress - ) -{ - *JumpAddress = PcdGet64(PcdFvBaseAddress); -} diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 0f8dd814ad15..81409b8f37ef 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -161,7 +161,6 @@ DEFINE DO_KCS = 1 PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf - ArmPlatformSecLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf

[edk2,3/6] Platforms/Styx: remove unused AmdStyxSecLib

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Patch