mbox

[PULL,00/94] target/sparc: Convert to decodetree

Message ID 20231026001542.1141412-1-richard.henderson@linaro.org
State New
Headers show

Pull-request

https://gitlab.com/rth7680/qemu.git tags/pull-sp-20231025

Message

Richard Henderson Oct. 26, 2023, 12:13 a.m. UTC 
The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:

  Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-sp-20231025

for you to fetch changes up to ba9c09b40b8e19ec50955216b61875d64042fa99:

  target/sparc: Remove disas_sparc_legacy (2023-10-25 01:01:13 -0700)

----------------------------------------------------------------
Convert target/sparc to decodetree.

----------------------------------------------------------------
Richard Henderson (94):
      target/sparc: Clear may_lookup for npc == DYNAMIC_PC
      target/sparc: Implement check_align inline
      target/sparc: Avoid helper_raise_exception in helper_st_asi
      target/sparc: Set TCG_GUEST_DEFAULT_MO
      configs: Enable MTTCG for sparc, sparc64
      target/sparc: Define features via cpu-feature.h.inc
      target/sparc: Use CPU_FEATURE_BIT_* for cpu properties
      target/sparc: Remove sparcv7 cpu features
      target/sparc: Partition cpu features
      target/sparc: Add decodetree infrastructure
      target/sparc: Define AM_CHECK for sparc32
      target/sparc: Move CALL to decodetree
      target/sparc: Move BPcc and Bicc to decodetree
      target/sparc: Move BPr to decodetree
      target/sparc: Move FBPfcc and FBfcc to decodetree
      target/sparc: Merge gen_cond with only caller
      target/sparc: Merge gen_fcond with only caller
      target/sparc: Merge gen_branch_[an] with only caller
      target/sparc: Pass DisasCompare to advance_jump_cond
      target/sparc: Move SETHI to decodetree
      target/sparc: Move Tcc to decodetree
      target/sparc: Move RDASR, STBAR, MEMBAR to decodetree
      target/sparc: Move RDPSR, RDHPR to decodetree
      target/sparc: Move RDWIM, RDPR to decodetree
      target/sparc: Move RDTBR, FLUSHW to decodetree
      target/sparc: Move WRASR to decodetree
      target/sparc: Move WRPSR, SAVED, RESTORED to decodetree
      target/sparc: Move WRWIM, WRPR to decodetree
      target/sparc: Move WRTBR, WRHPR to decodetree
      target/sparc: Remove cpu_wim
      target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr
      target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver
      target/sparc: Move basic arithmetic to decodetree
      target/sparc: Move ADDC to decodetree
      target/sparc: Move MULX to decodetree
      target/sparc: Move UMUL, SMUL to decodetree
      target/sparc: Move SUBC to decodetree
      target/sparc: Move UDIVX, SDIVX to decodetree
      target/sparc: Move UDIV, SDIV to decodetree
      target/sparc: Move TADD, TSUB, MULS to decodetree
      target/sparc: Move SLL, SRL, SRA to decodetree
      target/sparc: Move MOVcc, MOVR to decodetree
      target/sparc: Move POPC to decodetree
      target/sparc: Convert remaining v8 coproc insns to decodetree
      target/sparc: Move JMPL, RETT, RETURN to decodetree
      target/sparc: Move FLUSH, SAVE, RESTORE to decodetree
      target/sparc: Move DONE, RETRY to decodetree
      target/sparc: Split out resolve_asi
      target/sparc: Drop ifdef around get_asi and friends
      target/sparc: Split out ldst functions with asi pre-computed
      target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX
      target/sparc: Move simple integer load/store to decodetree
      target/sparc: Move asi integer load/store to decodetree
      target/sparc: Move LDSTUB, LDSTUBA to decodetree
      target/sparc: Move SWAP, SWAPA to decodetree
      target/sparc: Move CASA, CASXA to decodetree
      target/sparc: Move PREFETCH, PREFETCHA to decodetree
      target/sparc: Split out fp ldst functions with asi precomputed
      target/sparc: Move simple fp load/store to decodetree
      target/sparc: Move asi fp load/store to decodetree
      target/sparc: Move LDFSR, STFSR to decodetree
      target/sparc: Merge LDFSR, LDXFSR implementations
      target/sparc: Move EDGE* to decodetree
      target/sparc: Move ARRAY* to decodetree
      target/sparc: Move ADDRALIGN* to decodetree
      target/sparc: Move BMASK to decodetree
      target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree
      target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree
      target/sparc: Use tcg_gen_vec_{add,sub}*
      target/sparc: Move gen_ne_fop_FFF insns to decodetree
      target/sparc: Move gen_ne_fop_DDD insns to decodetree
      target/sparc: Move PDIST to decodetree
      target/sparc: Move gen_gsr_fop_DDD insns to decodetree
      target/sparc: Move gen_fop_FF insns to decodetree
      target/sparc: Move gen_fop_DD insns to decodetree
      target/sparc: Move FSQRTq to decodetree
      target/sparc: Move gen_fop_FFF insns to decodetree
      target/sparc: Move gen_fop_DDD insns to decodetree
      target/sparc: Move gen_fop_QQQ insns to decodetree
      target/sparc: Move FSMULD to decodetree
      target/sparc: Move FDMULQ to decodetree
      target/sparc: Move gen_fop_FD insns to decodetree
      target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
      target/sparc: Move FqTOs, FqTOi to decodetree
      target/sparc: Move FqTOd, FqTOx to decodetree
      target/sparc: Move FiTOq, FsTOq to decodetree
      target/sparc: Move FdTOq, FxTOq to decodetree
      target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
      target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
      target/sparc: Convert FCMP, FCMPE to decodetree
      target/sparc: Move FPCMP* to decodetree
      target/sparc: Move FPACK16, FPACKFIX to decodetree
      target/sparc: Convert FZERO, FONE to decodetree
      target/sparc: Remove disas_sparc_legacy

 configs/targets/sparc-softmmu.mak   |    1 +
 configs/targets/sparc64-softmmu.mak |    1 +
 linux-user/sparc/target_syscall.h   |    6 +-
 target/sparc/cpu.h                  |   76 +-
 target/sparc/helper.h               |   16 +-
 target/sparc/cpu-feature.h.inc      |   14 +
 target/sparc/insns.decode           |  547 +++
 target/sparc/cpu.c                  |   72 +-
 target/sparc/fop_helper.c           |   17 +-
 target/sparc/helper.c               |    8 -
 target/sparc/ldst_helper.c          |   17 +-
 target/sparc/translate.c            | 6971 +++++++++++++++++------------------
 target/sparc/vis_helper.c           |   59 -
 target/sparc/meson.build            |    3 +
 14 files changed, 4028 insertions(+), 3780 deletions(-)
 create mode 100644 target/sparc/cpu-feature.h.inc
 create mode 100644 target/sparc/insns.decode

Comments

Stefan Hajnoczi Oct. 27, 2023, 10:08 a.m. UTC | #1 
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.