Message ID | 20231030-ipq5332-nsscc-v1-3-6162a2c65f0a@quicinc.com |
---|---|
State | Superseded |
Headers | show
Return-Path: <linux-arm-msm-owner@vger.kernel.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C019CC4167B for <linux-arm-msm@archiver.kernel.org>; Mon, 30 Oct 2023 09:48:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232682AbjJ3JsL (ORCPT <rfc822;linux-arm-msm@archiver.kernel.org>); Mon, 30 Oct 2023 05:48:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232624AbjJ3JsE (ORCPT <rfc822;linux-arm-msm@vger.kernel.org>); Mon, 30 Oct 2023 05:48:04 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F68A122; Mon, 30 Oct 2023 02:47:55 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U8JFDq005590; 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Mon, 30 Oct 2023 09:47:46 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:40 -0700 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Date: Mon, 30 Oct 2023 15:17:18 +0530 Subject: [PATCH 3/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20231030-ipq5332-nsscc-v1-3-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Andy Gross <agross@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Richard Cochran <richardcochran@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org> CC: <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <netdev@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, "Kathiravan Thirumoorthy" <quic_kathirav@quicinc.com> X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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Series |
Add NSS clock controller support for IPQ5332
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expand
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diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 4649026da332..486b6cf2e916 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -176,6 +176,7 @@ #define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 #define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 #define GCC_USB0_PIPE_CLK_SRC 172 +#define GPLL0_OUT_AUX 173 #define GCC_ADSS_BCR 0 #define GCC_ADSS_PWM_CLK_ARES 1
Add the definition for GPLL0_OUT_AUX clock. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + 1 file changed, 1 insertion(+)