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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/realtek-dw-mshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DesignWare mobile storage host controller
+
+description:
+ Realtek uses the Synopsys DesignWare mobile storage host controller
+ to interface a SoC with storage medium. This file documents the Realtek
+ specific extensions.
+
+allOf:
+ - $ref: synopsys-dw-mshc-common.yaml#
+
+maintainers:
+ - Jyan Chou <jyanchou@realtek.com>
+
+properties:
+ compatible:
+ enum:
+ - realtek,rtd1325-dw-cqe-emmc
+
+ reg:
+ maxItems: 2
+ description:
+ Two regs are required, first reg specifies emmc base address, second reg
+ specifies cqhci base register address.
+
+ reg-names:
+ maxItems: 2
+ items:
+ - const: emmc
+ - const: cqhci
+
+ interrupts:
+ maxItems: 1
+
+ cqe:
+ maxItems: 1
+ description:
+ Cqe should set to 1 while using command queue feature, and set to 0 while
+ in legacy mode.
+
+ clocks:
+ minItems: 2
+ items:
+ - description: bus interface unit clock
+ - description: card interface unit clock
+ - description: select the phase for vpclk0 in realtek chip specified
+ - description: select the phase for vpclk1 in realtek chip specified
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: biu
+ - const: ciu
+ - const: vp0
+ - const: vp1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: reset
+
+ pinctrl-0:
+ description:
+ should contain default/high speed pin ctrl.
+ maxItems: 1
+
+ pinctrl-1:
+ description:
+ should contain sdr50 mode pin ctrl.
+ maxItems: 1
+
+ pinctrl-2:
+ description:
+ should contain ddr50 mode pin ctrl.
+ maxItems: 1
+
+ pinctrl-3:
+ description:
+ should contain hs200 speed pin ctrl.
+ maxItems: 1
+
+ pinctrl-4:
+ description:
+ should contain hs400 speed pin ctrl.
+ maxItems: 1
+
+ pinctrl-5:
+ description:
+ should contain tune0 pin ctrl.
+ maxItems: 1
+
+ pinctrl-6:
+ description:
+ should contain tune1 pin ctrl.
+ maxItems: 1
+
+ pinctrl-7:
+ description:
+ should contain tune2 pin ctrl.
+ maxItems: 1
+
+ pinctrl-8:
+ description:
+ should contain tune3 pin ctrl.
+ maxItems: 1
+
+ pinctrl-9:
+ description:
+ should contain tune4 pin ctrl.
+ maxItems: 1
+
+ pinctrl-names:
+ maxItems: 10
+
+ required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - pinctrl-names
+
+ unevaluatedProperties: false
+
+ examples:
+ - |
+ emmc: mmc@12000 {
+ compatible = "realtek,rtd1325-dw-cqe-emmc";
+ reg = <0x00012000 0x00600>,
+ <0x00012180 0x00060>;
+ reg-names = "emmc", "cqhci";
+ interrupts = <0 42 4>;
+ clocks = <&cc 22>, <&cc 26>, <&cc 121>, <&cc 122>;
+ clock-names = "biu", "ciu", "vp0", "vp1";
+ clock-freq-min-max = <300000 400000000>;
+ clock-frequency = <400000>;
+ vmmc-supply = <®_vcc1v8>;
+ resets = <&rst 20>;
+ reset-names = "reset";
+ speed-step = <3>;
+ cqe = <1>;
+ pinctrl-names = "default", "sdr50", "ddr50", "hs200", "hs400",
+ "tune0","tune1", "tune2","tune3", "tune4";
+ pinctrl-0 = <&emmc_pins_sdr50>;
+ pinctrl-1 = <&emmc_pins_sdr50>;
+ pinctrl-2 = <&emmc_pins_ddr50>;
+ pinctrl-3 = <&emmc_pins_hs200>;
+ pinctrl-4 = <&emmc_pins_hs400>;
+ pinctrl-5 = <&emmc_pins_tune0>;
+ pinctrl-6 = <&emmc_pins_tune1>;
+ pinctrl-7 = <&emmc_pins_tune2>;
+ pinctrl-8 = <&emmc_pins_tune3>;
+ pinctrl-9 = <&emmc_pins_tune4>;
+ };
Document the device-tree bindings for Realtek SoCs mmc driver. Signed-off-by: Jyan Chou <jyanchou@realtek.com> --- v3 -> v4: - Rename compatible(add SoC-specific part) to be different from filename. - Describe the items to make properties and item easy to understand. - Fix examples' indentation and compiling error. - Drop useless properties. v2 -> v3: - Modify dt-bindings' content and description. - Fix coding style. - Update the list of maintainers. v0 -> v2: - Add dt-bindings. --- --- .../bindings/mmc/realtek-dw-mshc.yaml | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/realtek-dw-mshc.yaml