| Message ID | 20231114-th1520-mmc-v6-5-3273c661a571@baylibre.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Add MMC support for TH1520 boards | expand |
On Tue, Nov 14, 2023 at 04:07:59PM -0500, Drew Fustini wrote: > + sdhci_clk: sdhci-clock { > + compatible = "fixed-clock"; > + clock-frequency = <198000000>; > + clock-output-names = "sdhci_clk"; > + #clock-cells = <0>; > + }; If only you had a clock driver to provide these... Is someone working on a resubmission of the clock driver?
On Tue, Nov 14, 2023 at 09:27:44PM +0000, Conor Dooley wrote: > On Tue, Nov 14, 2023 at 04:07:59PM -0500, Drew Fustini wrote: > > > + sdhci_clk: sdhci-clock { > > + compatible = "fixed-clock"; > > + clock-frequency = <198000000>; > > + clock-output-names = "sdhci_clk"; > > + #clock-cells = <0>; > > + }; > > If only you had a clock driver to provide these... > > Is someone working on a resubmission of the clock driver? Yangtao Li posted an initial revision back [1] in May but I don't think there has been any follow up. It is for sure something we need to have in mainline so I'll take a look at getting that effort going again. Drew [1] https://lore.kernel.org/linux-riscv/20230515054402.27633-1-frank.li@vivo.com/
On Tue, Nov 14, 2023 at 05:30:26PM -0500, Drew Fustini wrote: > On Tue, Nov 14, 2023 at 09:27:44PM +0000, Conor Dooley wrote: > > On Tue, Nov 14, 2023 at 04:07:59PM -0500, Drew Fustini wrote: > > > > > + sdhci_clk: sdhci-clock { > > > + compatible = "fixed-clock"; > > > + clock-frequency = <198000000>; > > > + clock-output-names = "sdhci_clk"; > > > + #clock-cells = <0>; > > > + }; > > > > If only you had a clock driver to provide these... > > > > Is someone working on a resubmission of the clock driver? > > Yangtao Li posted an initial revision back [1] in May but I don't think > there has been any follow up. It is for sure something we need to have > in mainline so I'll take a look at getting that effort going again. Hi Drew, Based on Yangtao's version, I cooked an updated version in last development window but still can't complete it and met some issues which need the clk/pll register document. IIRC, the document was released a few days ago before soc tree frozen. It's nice if you can continue the effort! I'll read the sdhci driver soon. Thanks > > Drew > > [1] https://lore.kernel.org/linux-riscv/20230515054402.27633-1-frank.li@vivo.com/
On Wed, Nov 15, 2023 at 11:22:03PM +0800, Jisheng Zhang wrote: > On Tue, Nov 14, 2023 at 05:30:26PM -0500, Drew Fustini wrote: > > On Tue, Nov 14, 2023 at 09:27:44PM +0000, Conor Dooley wrote: > > > On Tue, Nov 14, 2023 at 04:07:59PM -0500, Drew Fustini wrote: > > > > > > > + sdhci_clk: sdhci-clock { > > > > + compatible = "fixed-clock"; > > > > + clock-frequency = <198000000>; > > > > + clock-output-names = "sdhci_clk"; > > > > + #clock-cells = <0>; > > > > + }; > > > > > > If only you had a clock driver to provide these... > > > > > > Is someone working on a resubmission of the clock driver? > > > > Yangtao Li posted an initial revision back [1] in May but I don't think > > there has been any follow up. It is for sure something we need to have > > in mainline so I'll take a look at getting that effort going again. > > Hi Drew, > > Based on Yangtao's version, I cooked an updated version in last > development window but still can't complete it and met some issues > which need the clk/pll register document. > IIRC, the document was released a few days ago before soc tree frozen. > > It's nice if you can continue the effort! I'll read the sdhci driver > soon. PS: I can send my updated version to you for reference tomorrow. > > Thanks > > > > Drew > > > > [1] https://lore.kernel.org/linux-riscv/20230515054402.27633-1-frank.li@vivo.com/
On Wed, Nov 15, 2023 at 11:25:18PM +0800, Jisheng Zhang wrote: > On Wed, Nov 15, 2023 at 11:22:03PM +0800, Jisheng Zhang wrote: > > On Tue, Nov 14, 2023 at 05:30:26PM -0500, Drew Fustini wrote: > > > On Tue, Nov 14, 2023 at 09:27:44PM +0000, Conor Dooley wrote: > > > > On Tue, Nov 14, 2023 at 04:07:59PM -0500, Drew Fustini wrote: > > > > > > > > > + sdhci_clk: sdhci-clock { > > > > > + compatible = "fixed-clock"; > > > > > + clock-frequency = <198000000>; > > > > > + clock-output-names = "sdhci_clk"; > > > > > + #clock-cells = <0>; > > > > > + }; > > > > > > > > If only you had a clock driver to provide these... > > > > > > > > Is someone working on a resubmission of the clock driver? > > > > > > Yangtao Li posted an initial revision back [1] in May but I don't think > > > there has been any follow up. It is for sure something we need to have > > > in mainline so I'll take a look at getting that effort going again. > > > > Hi Drew, > > > > Based on Yangtao's version, I cooked an updated version in last > > development window but still can't complete it and met some issues > > which need the clk/pll register document. > > IIRC, the document was released a few days ago before soc tree frozen. > > > > It's nice if you can continue the effort! I'll read the sdhci driver > > soon. > > PS: I can send my updated version to you for reference tomorrow. Thank you, that would be great! Drew
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ff364709a6df..fb8a4a04d3c4 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,13 @@ uart_sclk: uart-sclk-clock { #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <198000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -292,6 +299,24 @@ dmac0: dma-controller@ffefc00000 { status = "disabled"; }; + mmc0: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + + mmc1: mmc@ffe7090000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7090000 0x0 0x10000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>;
Add node for the SDHCI fixed clock. Add mmc0 node for the first mmc controller instance which is typically connected to the eMMC device. Add mmc1 node for the second mmc controller instance which is typically connected to microSD slot. Signed-off-by: Drew Fustini <dfustini@baylibre.com> --- arch/riscv/boot/dts/thead/th1520.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)