@@ -1115,7 +1115,7 @@ spi0: spi@1100a000 {
lvts_ap: thermal-sensor@1100b000 {
compatible = "mediatek,mt8195-lvts-ap";
- reg = <0 0x1100b000 0 0x1000>;
+ reg = <0 0x1100b000 0 0xc00>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
@@ -1124,6 +1124,18 @@ lvts_ap: thermal-sensor@1100b000 {
#thermal-sensor-cells = <1>;
};
+ svs: svs@1100bc00 {
+ compatible = "mediatek,mt8195-svs";
+ reg = <0 0x1100bc00 0 0x400>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
+ nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+ resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
+ reset-names = "svs_rst";
+ };
+
disp_pwm0: pwm@1100e000 {
compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -1682,6 +1694,9 @@ lvts_efuse_data1: lvts1-calib@1bc {
lvts_efuse_data2: lvts2-calib@1d0 {
reg = <0x1d0 0x38>;
};
+ svs_calib_data: svs-calib@580 {
+ reg = <0x580 0x64>;
+ };
};
u3phy2: t-phy@11c40000 {
Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Also, reduce the LVTS_AP iospace to 0xc00, because that's exactly where SVS starts. - LVTS_AP start: 0x1100b000 length: 0xc00 - SVS start: 0x1100bc00 length: 0x400 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)