| Message ID | 20231126232746.264302-2-emil.renner.berthing@canonical.com |
|---|---|
| State | Accepted |
| Commit | 64fc984a8a54163a5c44e15a54b574a2c5564d8f |
| Headers | show |
| Series | [v1,1/8] riscv: errata: Add StarFive JH7100 errata | expand |
On Mon, Nov 27, 2023 at 12:27:39AM +0100, Emil Renner Berthing wrote: > This not really an errata, but since the JH7100 was made before > the standard Zicbom extension it needs the DMA_GLOBAL_POOL and > RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/Kconfig.errata | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata > index e2c731cfed8c..692de149141f 100644 > --- a/arch/riscv/Kconfig.errata > +++ b/arch/riscv/Kconfig.errata > @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 > > If you don't know what to do here, say "Y". > > +config ERRATA_STARFIVE_JH7100 > + bool "StarFive JH7100 support" > + depends on ARCH_STARFIVE && NONPORTABLE > + select DMA_GLOBAL_POOL > + select RISCV_DMA_NONCOHERENT > + select RISCV_NONSTANDARD_CACHE_OPS > + select SIFIVE_CCACHE > + default n > + help > + The StarFive JH7100 was a test chip for the JH7110 and has > + caches that are non-coherent with respect to peripheral DMAs. > + It was designed before the Zicbom extension so needs non-standard > + cache operations through the SiFive cache controller. > + > + Say "Y" if you want to support the BeagleV Starlight and/or > + StarFive VisionFive V1 boards. > + > config ERRATA_THEAD > bool "T-HEAD errata" > depends on RISCV_ALTERNATIVE > -- > 2.40.1 >
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e2c731cfed8c..692de149141f 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE_JH7100 + bool "StarFive JH7100 support" + depends on ARCH_STARFIVE && NONPORTABLE + select DMA_GLOBAL_POOL + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + select SIFIVE_CCACHE + default n + help + The StarFive JH7100 was a test chip for the JH7110 and has + caches that are non-coherent with respect to peripheral DMAs. + It was designed before the Zicbom extension so needs non-standard + cache operations through the SiFive cache controller. + + Say "Y" if you want to support the BeagleV Starlight and/or + StarFive VisionFive V1 boards. + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE
This not really an errata, but since the JH7100 was made before the standard Zicbom extension it needs the DMA_GLOBAL_POOL and RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- arch/riscv/Kconfig.errata | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)