| Message ID | 20231203154003.532765-1-amadeus@jmu.edu.cn |
|---|---|
| State | Accepted |
| Commit | 2e16f9dc9be07f08442d63d682cdf89d6321b408 |
| Headers | show |
| Series | [v2,1/1] arm64: dts: qcom: ipq6018: Add QUP5 SPI node | expand |
On Sun, 03 Dec 2023 23:40:03 +0800, Chukun Pan wrote: > Add node to support the QUP5 SPI controller inside of IPQ6018. > Some routers use this bus to connect SPI TPM chips. > > Applied, thanks! [1/1] arm64: dts: qcom: ipq6018: Add QUP5 SPI node commit: 2e16f9dc9be07f08442d63d682cdf89d6321b408 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index ec0a0ce1849e..2399d16f147e 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -527,6 +527,20 @@ blsp1_spi2: spi@78b6000 { status = "disabled"; }; + blsp1_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x078b9000 0x0 0x600>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>;
Add node to support the QUP5 SPI controller inside of IPQ6018. Some routers use this bus to connect SPI TPM chips. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> --- Changes in v2: * No changes, resend due to error link to other threads. arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)