| Message ID | 20231208065902.11006-15-manivannan.sadhasivam@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | scsi: ufs: qcom: Code cleanups | expand |
On Fri, Dec 08, 2023 at 12:28:59PM +0530, Manivannan Sadhasivam wrote: > In both the functions, UFS_PHY_SOFT_RESET contains the mask of the reset > bit. So this can be passed directly as the value to be written for > asserting the reset. For deasserting, 0 can be passed. > > This gets rid of the FIELD_PREP() inside these functions and also > UFS_PHY_RESET_{ENABLE/DISABLE} definitions. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> > --- > drivers/ufs/host/ufs-qcom.h | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h > index 53db424a0bcb..a109d3359db4 100644 > --- a/drivers/ufs/host/ufs-qcom.h > +++ b/drivers/ufs/host/ufs-qcom.h > @@ -92,9 +92,6 @@ enum { > #define TEST_BUS_SEL GENMASK(22, 19) > #define UFS_REG_TEST_BUS_EN BIT(30) > > -#define UFS_PHY_RESET_ENABLE 1 > -#define UFS_PHY_RESET_DISABLE 0 > - > /* bit definitions for REG_UFS_CFG2 register */ > #define UAWM_HW_CGC_EN BIT(0) > #define UARM_HW_CGC_EN BIT(1) > @@ -157,8 +154,7 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, > > static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) > { > - ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE), > - REG_UFS_CFG1); > + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); > > /* > * Make sure assertion of ufs phy reset is written to > @@ -169,8 +165,7 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) > > static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) > { > - ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE), > - REG_UFS_CFG1); > + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); > > /* > * Make sure de-assertion of ufs phy reset is written to > -- > 2.25.1 >
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 53db424a0bcb..a109d3359db4 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -92,9 +92,6 @@ enum { #define TEST_BUS_SEL GENMASK(22, 19) #define UFS_REG_TEST_BUS_EN BIT(30) -#define UFS_PHY_RESET_ENABLE 1 -#define UFS_PHY_RESET_DISABLE 0 - /* bit definitions for REG_UFS_CFG2 register */ #define UAWM_HW_CGC_EN BIT(0) #define UARM_HW_CGC_EN BIT(1) @@ -157,8 +154,7 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE), - REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); /* * Make sure assertion of ufs phy reset is written to @@ -169,8 +165,7 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE), - REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); /* * Make sure de-assertion of ufs phy reset is written to
In both the functions, UFS_PHY_SOFT_RESET contains the mask of the reset bit. So this can be passed directly as the value to be written for asserting the reset. For deasserting, 0 can be passed. This gets rid of the FIELD_PREP() inside these functions and also UFS_PHY_RESET_{ENABLE/DISABLE} definitions. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/ufs/host/ufs-qcom.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)