@@ -107,11 +107,11 @@
* DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode.
* Debug mode is determined by the DBGACK CPU signal.
*/
-#define QUIRK_HAS_WTCLRINT_REG (1 << 0)
-#define QUIRK_HAS_PMU_MASK_RESET (1 << 1)
-#define QUIRK_HAS_PMU_RST_STAT (1 << 2)
-#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
-#define QUIRK_HAS_PMU_CNT_EN (1 << 4)
+#define QUIRK_HAS_WTCLRINT_REG BIT(0)
+#define QUIRK_HAS_PMU_MASK_RESET BIT(1)
+#define QUIRK_HAS_PMU_RST_STAT BIT(2)
+#define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3)
+#define QUIRK_HAS_PMU_CNT_EN BIT(4)
#define QUIRK_HAS_DBGACK_BIT BIT(5)
/* These quirks require that we have a PMU register map */
Update the remaining QUIRK macros to use the BIT macro. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- drivers/watchdog/s3c2410_wdt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)