| Message ID | 20231218113305.2511480-22-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement emulation of nested virtualization | expand |
On 12/18/23 22:32, Peter Maydell wrote: > Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the > Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2 > support to FEAT_NV for the latter two CPU types. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > docs/system/arm/emulation.rst | 1 + > target/arm/cpu.c | 8 +++++--- > target/arm/tcg/cpu64.c | 1 + > 3 files changed, 7 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
W dniu 18.12.2023 o 12:32, Peter Maydell pisze: > Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the > Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2 > support to FEAT_NV for the latter two CPU types. According to Neoverse-V1 TRM r1p2 it has FEAT_NV2. Similar with Neoverse-N2. You wrote already: > in practice hypervisors such as KVM are going to require FEAT_NV2 > and not bother to support the FEAT_NV-only case, so I have > implemented them one after the other in this single patchset. So maybe they both should be FEAT_NV2 and FEAT_NV will be left unused. Or enable FEAT_NV for V1 (as being older) and FEAT_NV2 on N2. This way if someone wants to test nested virtualization then both versions will be available without use of 'max' cpu.
On Fri, 29 Dec 2023 at 11:37, Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> wrote: > > W dniu 18.12.2023 o 12:32, Peter Maydell pisze: > > > Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the > > Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2 > > support to FEAT_NV for the latter two CPU types. > > According to Neoverse-V1 TRM r1p2 it has FEAT_NV2. Similar with Neoverse-N2. I'm not sure what you're trying to say here ? Yes, the V1 has NV2, that's why we have to downgrade it to FEAT_NV for the moment when we're emulating, because at this point in the series we don't have FEAT_NV2 emulation. At the end of the series this downgrade goes away, because at that point we can emulate FEAT_NV2. > > You wrote already: > > > in practice hypervisors such as KVM are going to require FEAT_NV2 > > and not bother to support the FEAT_NV-only case, so I have > > implemented them one after the other in this single patchset. > So maybe they both should be FEAT_NV2 and FEAT_NV will be left unused. > Or enable FEAT_NV for V1 (as being older) and FEAT_NV2 on N2. As usual, we emulate what the actual hardware has, to the extent that we are able to. For both of these CPUs that's both FEAT_NV and FEAT_NV2, and we enable emulation of each at the point in the series when we've implemented it. > This way if someone wants to test nested virtualization then both > versions will be available without use of 'max' cpu. In theory it might be nice to be able to emulate a pure FEAT_NV CPU, but in practice I don't expect anybody to want to do that. If anybody has a real use case for it we can add a -cpu suboption later. thanks -- PMM
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0b604f90059..d827b42de79 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -63,6 +63,7 @@ the following architecture extensions: - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) +- FEAT_NV (Nested Virtualization) - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) - FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm) - FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index efb22a87f9e..da0c02f850b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2238,9 +2238,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); - /* FEAT_NV (Nested Virtualization) */ - cpu->isar.id_aa64mmfr2 = - FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); + /* FEAT_NV2 (Enhanced Nested Virtualization support) */ + if (FIELD_EX64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV) > 1) { + cpu->isar.id_aa64mmfr2 = + FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 1); + } } /* MPU can be configured out of a PMSA CPU either by setting has-mpu diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 40e7a45166f..93f040e6e96 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1204,6 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t = FIELD_DP64(t, ID_AA64MMFR2, NV, 1); /* FEAT_NV */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2 support to FEAT_NV for the latter two CPU types. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 8 +++++--- target/arm/tcg/cpu64.c | 1 + 3 files changed, 7 insertions(+), 3 deletions(-)