| Message ID | 20231223-x1e80100-phy-pcie-v2-2-223c0556908a@linaro.org |
|---|---|
| State | Accepted |
| Commit | 70e0af37e81e8a19e207ccf14953109d793087cb |
| Headers | show |
| Series | phy: qcom: qmp-pcie: Add support for G3/G4 PCIe PHY for X1E80100 | expand |
On Sat, 23 Dec 2023 at 13:55, Abel Vesa <abel.vesa@linaro.org> wrote: > > For consistency, add the QMP v6 registers layout even though > they are the same as v5. Also switch all QMP v6 PHYs to use this > new layout. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) On Thu, 21 Dec 2023 at 05:51, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > The SA8295P and SA8540P uses an external regulator (max20411), and > gfx.lvl is not provided by rpmh. Drop the power-domains property of the > gpucc node to reflect this. > > Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes") > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sa8540p.dtsi | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Sun, 24 Dec 2023 at 08:16, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On Sat, 23 Dec 2023 at 13:55, Abel Vesa <abel.vesa@linaro.org> wrote: > > > > For consistency, add the QMP v6 registers layout even though > > they are the same as v5. Also switch all QMP v6 PHYs to use this > > new layout. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 ++++++++++--- > > 1 file changed, 10 insertions(+), 3 deletions(-) > > On Thu, 21 Dec 2023 at 05:51, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > > > The SA8295P and SA8540P uses an external regulator (max20411), and > > gfx.lvl is not provided by rpmh. Drop the power-domains property of the > > gpucc node to reflect this. > > > > Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes") > > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/sa8540p.dtsi | 2 ++ > > 1 file changed, 2 insertions(+) To resolve possible questions, the lines above got c&p-ed from another email. The R-B tag is applicable to the patch in question (v6 regs layout). > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > -- > With best wishes > Dmitry
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2af7115ef968..03a4898a7e6f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -116,6 +116,13 @@ static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, }; +static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -2936,7 +2943,7 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS_4_20, @@ -3069,7 +3076,7 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, @@ -3099,7 +3106,7 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20,
For consistency, add the QMP v6 registers layout even though they are the same as v5. Also switch all QMP v6 PHYs to use this new layout. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)