diff mbox series

[v2,1/2] mpt3sas: Reload SBR without rebooting HBA

Message ID 20231227110610.18276-2-ranjan.kumar@broadcom.com
State Superseded
Headers show
Series mpt3sas: Update/reload SBR without rebooting HBA | expand

Commit Message

Ranjan Kumar Dec. 27, 2023, 11:06 a.m. UTC
Added a new IOCTL command MPT3ENABLEDIAGSBRRELOAD.
As a part of firmware update operation, applications use this IOCTL
command to set the SBR reload bit in the Host Diagnostic register.
So that HBA firmware is updated without power-cycling the system.

Signed-off-by: Ranjan Kumar <ranjan.kumar@broadcom.com>
---
 drivers/scsi/mpt3sas/mpt3sas_base.c  | 97 +++++++++++++++++++---------
 drivers/scsi/mpt3sas/mpt3sas_base.h  |  4 ++
 drivers/scsi/mpt3sas/mpt3sas_ctl.c   | 54 ++++++++++++++++
 drivers/scsi/mpt3sas/mpt3sas_ctl.h   | 10 +++
 drivers/scsi/mpt3sas/mpt3sas_scsih.c |  1 +
 5 files changed, 135 insertions(+), 31 deletions(-)

Comments

kernel test robot Dec. 28, 2023, 1:53 a.m. UTC | #1
Hi Ranjan,

kernel test robot noticed the following build warnings:

[auto build test WARNING on jejb-scsi/for-next]
[also build test WARNING on mkp-scsi/for-next linus/master v6.7-rc7 next-20231222]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ranjan-Kumar/mpt3sas-Reload-SBR-without-rebooting-HBA/20231227-191013
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git for-next
patch link:    https://lore.kernel.org/r/20231227110610.18276-2-ranjan.kumar%40broadcom.com
patch subject: [PATCH v2 1/2] mpt3sas: Reload SBR without rebooting HBA
config: x86_64-allmodconfig (https://download.01.org/0day-ci/archive/20231228/202312280909.MZyhxwBL-lkp@intel.com/config)
compiler: ClangBuiltLinux clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231228/202312280909.MZyhxwBL-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312280909.MZyhxwBL-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/scsi/mpt3sas/mpt3sas_base.c:8025:4: warning: misleading indentation; statement is not part of the previous 'if' [-Wmisleading-indentation]
    8025 |                         msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC/1000);
         |                         ^
   drivers/scsi/mpt3sas/mpt3sas_base.c:8021:3: note: previous statement is here
    8021 |                 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
         |                 ^
   1 warning generated.


vim +/if +8025 drivers/scsi/mpt3sas/mpt3sas_base.c

2af5cddbc76400 Ranjan Kumar     2023-12-27  7976  
2af5cddbc76400 Ranjan Kumar     2023-12-27  7977  /**
2af5cddbc76400 Ranjan Kumar     2023-12-27  7978   * _base_diag_reset - the "big hammer" start of day reset
2af5cddbc76400 Ranjan Kumar     2023-12-27  7979   * @ioc: per adapter object
2af5cddbc76400 Ranjan Kumar     2023-12-27  7980   *
2af5cddbc76400 Ranjan Kumar     2023-12-27  7981   * Return: 0 for success, non-zero for failure.
2af5cddbc76400 Ranjan Kumar     2023-12-27  7982   */
2af5cddbc76400 Ranjan Kumar     2023-12-27  7983  static int
2af5cddbc76400 Ranjan Kumar     2023-12-27  7984  _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
2af5cddbc76400 Ranjan Kumar     2023-12-27  7985  {
2af5cddbc76400 Ranjan Kumar     2023-12-27  7986  	u32 host_diagnostic;
2af5cddbc76400 Ranjan Kumar     2023-12-27  7987  	u32 ioc_state;
2af5cddbc76400 Ranjan Kumar     2023-12-27  7988  	u32 count;
2af5cddbc76400 Ranjan Kumar     2023-12-27  7989  	u32 hcb_size;
2af5cddbc76400 Ranjan Kumar     2023-12-27  7990  
2af5cddbc76400 Ranjan Kumar     2023-12-27  7991  	ioc_info(ioc, "sending diag reset !!\n");
2af5cddbc76400 Ranjan Kumar     2023-12-27  7992  
2af5cddbc76400 Ranjan Kumar     2023-12-27  7993  	pci_cfg_access_lock(ioc->pdev);
f92363d1235949 Sreekanth Reddy  2012-11-30  7994  
2af5cddbc76400 Ranjan Kumar     2023-12-27  7995  	drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
2af5cddbc76400 Ranjan Kumar     2023-12-27  7996  
2af5cddbc76400 Ranjan Kumar     2023-12-27  7997  	mutex_lock(&ioc->hostdiag_unlock_mutex);
2af5cddbc76400 Ranjan Kumar     2023-12-27  7998  	if (mpt3sas_base_unlock_and_get_host_diagnostic(ioc, &host_diagnostic))
2af5cddbc76400 Ranjan Kumar     2023-12-27  7999  		goto out;
2af5cddbc76400 Ranjan Kumar     2023-12-27  8000  
2af5cddbc76400 Ranjan Kumar     2023-12-27  8001  	hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
919d8a3f3fef99 Joe Perches      2018-09-17  8002  	drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
f92363d1235949 Sreekanth Reddy  2012-11-30  8003  	writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
f92363d1235949 Sreekanth Reddy  2012-11-30  8004  	     &ioc->chip->HostDiagnostic);
f92363d1235949 Sreekanth Reddy  2012-11-30  8005  
b453ff84de6caf Sreekanth Reddy  2013-06-29  8006  	/* This delay allows the chip PCIe hardware time to finish reset tasks */
b453ff84de6caf Sreekanth Reddy  2013-06-29  8007  	msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
f92363d1235949 Sreekanth Reddy  2012-11-30  8008  
b453ff84de6caf Sreekanth Reddy  2013-06-29  8009  	/* Approximately 300 second max wait */
b453ff84de6caf Sreekanth Reddy  2013-06-29  8010  	for (count = 0; count < (300000000 /
b453ff84de6caf Sreekanth Reddy  2013-06-29  8011  	    MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
f92363d1235949 Sreekanth Reddy  2012-11-30  8012  
4ca10f3e31745d Ranjan Kumar     2023-08-29  8013  		host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
f92363d1235949 Sreekanth Reddy  2012-11-30  8014  
5b061980e36282 Sreekanth Reddy  2019-12-26  8015  		if (host_diagnostic == 0xFFFFFFFF) {
5b061980e36282 Sreekanth Reddy  2019-12-26  8016  			ioc_info(ioc,
5b061980e36282 Sreekanth Reddy  2019-12-26  8017  			    "Invalid host diagnostic register value\n");
af6ec1eee5ed68 Suganath Prabu S 2020-07-30  8018  			_base_dump_reg_set(ioc);
f92363d1235949 Sreekanth Reddy  2012-11-30  8019  			goto out;
5b061980e36282 Sreekanth Reddy  2019-12-26  8020  		}
f92363d1235949 Sreekanth Reddy  2012-11-30  8021  		if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
f92363d1235949 Sreekanth Reddy  2012-11-30  8022  			break;
f92363d1235949 Sreekanth Reddy  2012-11-30  8023  
2af5cddbc76400 Ranjan Kumar     2023-12-27  8024  		/* Wait to pass the second read delay window */
98c56ad32c33f0 Calvin Owens     2016-07-28 @8025  			msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC/1000);
f92363d1235949 Sreekanth Reddy  2012-11-30  8026  	}
f92363d1235949 Sreekanth Reddy  2012-11-30  8027  
f92363d1235949 Sreekanth Reddy  2012-11-30  8028  	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
f92363d1235949 Sreekanth Reddy  2012-11-30  8029  
919d8a3f3fef99 Joe Perches      2018-09-17  8030  		drsprintk(ioc,
2af5cddbc76400 Ranjan Kumar     2023-12-27  8031  			ioc_info(ioc, "restart the adapter assuming the\n"
2af5cddbc76400 Ranjan Kumar     2023-12-27  8032  					"HCB Address points to good F/W\n"));
f92363d1235949 Sreekanth Reddy  2012-11-30  8033  		host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
f92363d1235949 Sreekanth Reddy  2012-11-30  8034  		host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
f92363d1235949 Sreekanth Reddy  2012-11-30  8035  		writel(host_diagnostic, &ioc->chip->HostDiagnostic);
f92363d1235949 Sreekanth Reddy  2012-11-30  8036  
919d8a3f3fef99 Joe Perches      2018-09-17  8037  		drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
f92363d1235949 Sreekanth Reddy  2012-11-30  8038  		writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
f92363d1235949 Sreekanth Reddy  2012-11-30  8039  		    &ioc->chip->HCBSize);
f92363d1235949 Sreekanth Reddy  2012-11-30  8040  	}
f92363d1235949 Sreekanth Reddy  2012-11-30  8041  
919d8a3f3fef99 Joe Perches      2018-09-17  8042  	drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
f92363d1235949 Sreekanth Reddy  2012-11-30  8043  	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
f92363d1235949 Sreekanth Reddy  2012-11-30  8044  	    &ioc->chip->HostDiagnostic);
f92363d1235949 Sreekanth Reddy  2012-11-30  8045  
2af5cddbc76400 Ranjan Kumar     2023-12-27  8046  	mpt3sas_base_lock_host_diagnostic(ioc);
2af5cddbc76400 Ranjan Kumar     2023-12-27  8047  	mutex_unlock(&ioc->hostdiag_unlock_mutex);
f92363d1235949 Sreekanth Reddy  2012-11-30  8048  
919d8a3f3fef99 Joe Perches      2018-09-17  8049  	drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
98c56ad32c33f0 Calvin Owens     2016-07-28  8050  	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
f92363d1235949 Sreekanth Reddy  2012-11-30  8051  	if (ioc_state) {
919d8a3f3fef99 Joe Perches      2018-09-17  8052  		ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
919d8a3f3fef99 Joe Perches      2018-09-17  8053  			__func__, ioc_state);
af6ec1eee5ed68 Suganath Prabu S 2020-07-30  8054  		_base_dump_reg_set(ioc);
f92363d1235949 Sreekanth Reddy  2012-11-30  8055  		goto out;
f92363d1235949 Sreekanth Reddy  2012-11-30  8056  	}
f92363d1235949 Sreekanth Reddy  2012-11-30  8057  
3c8604691d2acc Sreekanth Reddy  2021-03-30  8058  	pci_cfg_access_unlock(ioc->pdev);
919d8a3f3fef99 Joe Perches      2018-09-17  8059  	ioc_info(ioc, "diag reset: SUCCESS\n");
f92363d1235949 Sreekanth Reddy  2012-11-30  8060  	return 0;
f92363d1235949 Sreekanth Reddy  2012-11-30  8061  
f92363d1235949 Sreekanth Reddy  2012-11-30  8062   out:
3c8604691d2acc Sreekanth Reddy  2021-03-30  8063  	pci_cfg_access_unlock(ioc->pdev);
919d8a3f3fef99 Joe Perches      2018-09-17  8064  	ioc_err(ioc, "diag reset: FAILED\n");
2af5cddbc76400 Ranjan Kumar     2023-12-27  8065  	mutex_unlock(&ioc->hostdiag_unlock_mutex);
f92363d1235949 Sreekanth Reddy  2012-11-30  8066  	return -EFAULT;
f92363d1235949 Sreekanth Reddy  2012-11-30  8067  }
f92363d1235949 Sreekanth Reddy  2012-11-30  8068
kernel test robot Dec. 28, 2023, 3:56 a.m. UTC | #2
Hi Ranjan,

kernel test robot noticed the following build warnings:

[auto build test WARNING on jejb-scsi/for-next]
[also build test WARNING on mkp-scsi/for-next linus/master v6.7-rc7 next-20231222]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ranjan-Kumar/mpt3sas-Reload-SBR-without-rebooting-HBA/20231227-191013
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git for-next
patch link:    https://lore.kernel.org/r/20231227110610.18276-2-ranjan.kumar%40broadcom.com
patch subject: [PATCH v2 1/2] mpt3sas: Reload SBR without rebooting HBA
config: x86_64-randconfig-161-20231228 (https://download.01.org/0day-ci/archive/20231228/202312281141.jDyPezRn-lkp@intel.com/config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231228/202312281141.jDyPezRn-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312281141.jDyPezRn-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/scsi/mpt3sas/mpt3sas_ctl.c:2555: warning: Function parameter or member 'arg' not described in '_ctl_enable_diag_sbr_reload'


vim +2555 drivers/scsi/mpt3sas/mpt3sas_ctl.c

  2545	
  2546	/**
  2547	 * _ctl_enable_diag_sbr_reload - enable sbr reload bit
  2548	 * @ioc: per adapter object
  2549	 * @arg - user space buffer containing ioctl content
  2550	 *
  2551	 * Enable the SBR reload bit
  2552	 */
  2553	static int
  2554	_ctl_enable_diag_sbr_reload(struct MPT3SAS_ADAPTER *ioc, void __user *arg)
> 2555	{
  2556		u32 ioc_state, host_diagnostic;
  2557	
  2558		if (ioc->shost_recovery ||
  2559		    ioc->pci_error_recovery || ioc->is_driver_loading ||
  2560		    ioc->remove_host)
  2561			return -EAGAIN;
  2562	
  2563		ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  2564	
  2565		if (ioc_state != MPI2_IOC_STATE_OPERATIONAL)
  2566			return -EFAULT;
  2567	
  2568		host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
  2569	
  2570		if (host_diagnostic & MPI2_DIAG_SBR_RELOAD)
  2571			return 0;
  2572	
  2573		if (mutex_trylock(&ioc->hostdiag_unlock_mutex)) {
  2574			if (mpt3sas_base_unlock_and_get_host_diagnostic(ioc, &host_diagnostic)) {
  2575				mutex_unlock(&ioc->hostdiag_unlock_mutex);
  2576					return -EFAULT;
  2577			}
  2578		} else
  2579			return -EAGAIN;
  2580	
  2581		host_diagnostic |= MPI2_DIAG_SBR_RELOAD;
  2582		writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  2583		host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
  2584		mpt3sas_base_lock_host_diagnostic(ioc);
  2585		mutex_unlock(&ioc->hostdiag_unlock_mutex);
  2586	
  2587		if (!(host_diagnostic & MPI2_DIAG_SBR_RELOAD)) {
  2588			ioc_err(ioc, "%s: Failed to set Diag SBR Reload Bit\n", __func__);
  2589			return -EFAULT;
  2590		}
  2591	
  2592		ioc_info(ioc, "%s: Successfully set the Diag SBR Reload Bit\n", __func__);
  2593		return 0;
  2594	}
  2595
diff mbox series

Patch

diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 8761bc58d965..da1497cadeb1 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -7914,26 +7914,22 @@  mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
 }
 
 /**
- * _base_diag_reset - the "big hammer" start of day reset
- * @ioc: per adapter object
- *
- * Return: 0 for success, non-zero for failure.
- */
-static int
-_base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
-{
-	u32 host_diagnostic;
-	u32 ioc_state;
-	u32 count;
-	u32 hcb_size;
-
-	ioc_info(ioc, "sending diag reset !!\n");
-
-	pci_cfg_access_lock(ioc->pdev);
+* mpt3sas_base_unlock_and_get_host_diagnostic- enable Host Diagnostic Register writes
+* @ioc: per adapter object
+* @host_diagnostic: host diagnostic register content
+*
+* Return: 0 for success, non-zero for failure.
+*/
 
-	drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
+int
+mpt3sas_base_unlock_and_get_host_diagnostic(struct MPT3SAS_ADAPTER *ioc,
+	u32 *host_diagnostic)
+{
 
+	u32 count;
+	*host_diagnostic = 0;
 	count = 0;
+
 	do {
 		/* Write magic sequence to WriteSequence register
 		 * Loop until in diagnostic mode
@@ -7952,30 +7948,67 @@  _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
 
 		if (count++ > 20) {
 			ioc_info(ioc,
-			    "Stop writing magic sequence after 20 retries\n");
+				    "Stop writing magic sequence after 20 retries\n");
 			_base_dump_reg_set(ioc);
-			goto out;
+			return -EFAULT;
 		}
 
-		host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
+		*host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
 		drsprintk(ioc,
-			  ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
-				   count, host_diagnostic));
+			     ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
+				     count, *host_diagnostic));
 
-	} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
+	} while ((*host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
+	return 0;
+}
 
-	hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
+/**
+ * mpt3sas_base_lock_host_diagnostic: Disable Host Diagnostic Register writes
+ * @ioc: per adapter object
+ */
 
+void
+mpt3sas_base_lock_host_diagnostic(struct MPT3SAS_ADAPTER *ioc)
+{
+	drsprintk(ioc, ioc_info(ioc, "disable writes to the diagnostic register\n"));
+	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
+}
+
+/**
+ * _base_diag_reset - the "big hammer" start of day reset
+ * @ioc: per adapter object
+ *
+ * Return: 0 for success, non-zero for failure.
+ */
+static int
+_base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
+{
+	u32 host_diagnostic;
+	u32 ioc_state;
+	u32 count;
+	u32 hcb_size;
+
+	ioc_info(ioc, "sending diag reset !!\n");
+
+	pci_cfg_access_lock(ioc->pdev);
+
+	drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
+
+	mutex_lock(&ioc->hostdiag_unlock_mutex);
+	if (mpt3sas_base_unlock_and_get_host_diagnostic(ioc, &host_diagnostic))
+		goto out;
+
+	hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
 	drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
 	writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
 	     &ioc->chip->HostDiagnostic);
 
-	/*This delay allows the chip PCIe hardware time to finish reset tasks*/
+	/* This delay allows the chip PCIe hardware time to finish reset tasks */
 	msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
 
 	/* Approximately 300 second max wait */
 	for (count = 0; count < (300000000 /
-		MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
+	    MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
 
 		host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic);
 
@@ -7988,13 +8021,15 @@  _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
 		if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
 			break;
 
-		msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
+		/* Wait to pass the second read delay window */
+			msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC/1000);
 	}
 
 	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
 
 		drsprintk(ioc,
-			  ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
+			ioc_info(ioc, "restart the adapter assuming the\n"
+					"HCB Address points to good F/W\n"));
 		host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
 		host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
 		writel(host_diagnostic, &ioc->chip->HostDiagnostic);
@@ -8008,9 +8043,8 @@  _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
 	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
 	    &ioc->chip->HostDiagnostic);
 
-	drsprintk(ioc,
-		  ioc_info(ioc, "disable writes to the diagnostic register\n"));
-	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
+	mpt3sas_base_lock_host_diagnostic(ioc);
+	mutex_unlock(&ioc->hostdiag_unlock_mutex);
 
 	drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
 	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
@@ -8028,6 +8062,7 @@  _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
  out:
 	pci_cfg_access_unlock(ioc->pdev);
 	ioc_err(ioc, "diag reset: FAILED\n");
+	mutex_unlock(&ioc->hostdiag_unlock_mutex);
 	return -EFAULT;
 }
 
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
index 6d0bc8c66700..de60ef8a7908 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
@@ -1366,6 +1366,7 @@  struct MPT3SAS_ADAPTER {
 	u8		got_task_abort_from_ioctl;
 
 	struct mutex	reset_in_progress_mutex;
+	struct mutex    hostdiag_unlock_mutex;
 	spinlock_t	ioc_reset_in_progress_lock;
 	u8		ioc_link_reset_in_progress;
 
@@ -1790,6 +1791,9 @@  void mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc);
 int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
 void mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc);
 void mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc);
+int mpt3sas_base_unlock_and_get_host_diagnostic(struct MPT3SAS_ADAPTER *ioc,
+	u32 *host_diagnostic);
+void mpt3sas_base_lock_host_diagnostic(struct MPT3SAS_ADAPTER *ioc);
 
 /* scsih shared API */
 struct scsi_cmnd *mpt3sas_scsih_scsi_lookup_get(struct MPT3SAS_ADAPTER *ioc,
diff --git a/drivers/scsi/mpt3sas/mpt3sas_ctl.c b/drivers/scsi/mpt3sas/mpt3sas_ctl.c
index 147cb7088d55..5299dc297c04 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_ctl.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_ctl.c
@@ -2543,6 +2543,56 @@  _ctl_addnl_diag_query(struct MPT3SAS_ADAPTER *ioc, void __user *arg)
 	return 0;
 }
 
+/**
+ * _ctl_enable_diag_sbr_reload - enable sbr reload bit
+ * @ioc: per adapter object
+ * @arg - user space buffer containing ioctl content
+ *
+ * Enable the SBR reload bit
+ */
+static int
+_ctl_enable_diag_sbr_reload(struct MPT3SAS_ADAPTER *ioc, void __user *arg)
+{
+	u32 ioc_state, host_diagnostic;
+
+	if (ioc->shost_recovery ||
+	    ioc->pci_error_recovery || ioc->is_driver_loading ||
+	    ioc->remove_host)
+		return -EAGAIN;
+
+	ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
+
+	if (ioc_state != MPI2_IOC_STATE_OPERATIONAL)
+		return -EFAULT;
+
+	host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
+
+	if (host_diagnostic & MPI2_DIAG_SBR_RELOAD)
+		return 0;
+
+	if (mutex_trylock(&ioc->hostdiag_unlock_mutex)) {
+		if (mpt3sas_base_unlock_and_get_host_diagnostic(ioc, &host_diagnostic)) {
+			mutex_unlock(&ioc->hostdiag_unlock_mutex);
+				return -EFAULT;
+		}
+	} else
+		return -EAGAIN;
+
+	host_diagnostic |= MPI2_DIAG_SBR_RELOAD;
+	writel(host_diagnostic, &ioc->chip->HostDiagnostic);
+	host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
+	mpt3sas_base_lock_host_diagnostic(ioc);
+	mutex_unlock(&ioc->hostdiag_unlock_mutex);
+
+	if (!(host_diagnostic & MPI2_DIAG_SBR_RELOAD)) {
+		ioc_err(ioc, "%s: Failed to set Diag SBR Reload Bit\n", __func__);
+		return -EFAULT;
+	}
+
+	ioc_info(ioc, "%s: Successfully set the Diag SBR Reload Bit\n", __func__);
+	return 0;
+}
+
 #ifdef CONFIG_COMPAT
 /**
  * _ctl_compat_mpt_command - convert 32bit pointers to 64bit.
@@ -2719,6 +2769,10 @@  _ctl_ioctl_main(struct file *file, unsigned int cmd, void __user *arg,
 		if (_IOC_SIZE(cmd) == sizeof(struct mpt3_addnl_diag_query))
 			ret = _ctl_addnl_diag_query(ioc, arg);
 		break;
+	case MPT3ENABLEDIAGSBRRELOAD:
+		if (_IOC_SIZE(cmd) == sizeof(struct mpt3_enable_diag_sbr_reload))
+			ret = _ctl_enable_diag_sbr_reload(ioc, arg);
+		break;
 	default:
 		dctlprintk(ioc,
 			   ioc_info(ioc, "unsupported ioctl opcode(0x%08x)\n",
diff --git a/drivers/scsi/mpt3sas/mpt3sas_ctl.h b/drivers/scsi/mpt3sas/mpt3sas_ctl.h
index 8f6ffb40261c..171709e91006 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_ctl.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_ctl.h
@@ -98,6 +98,8 @@ 
 	struct mpt3_diag_read_buffer)
 #define MPT3ADDNLDIAGQUERY _IOWR(MPT3_MAGIC_NUMBER, 32, \
 	struct mpt3_addnl_diag_query)
+#define MPT3ENABLEDIAGSBRRELOAD _IOWR(MPT3_MAGIC_NUMBER, 33, \
+	struct mpt3_enable_diag_sbr_reload)
 
 /* Trace Buffer default UniqueId */
 #define MPT2DIAGBUFFUNIQUEID (0x07075900)
@@ -448,4 +450,12 @@  struct mpt3_addnl_diag_query {
 	uint32_t reserved2[2];
 };
 
+/**
+ * struct mpt3_enable_diag_sbr_reload - enable sbr reload
+ * @hdr - generic header
+ */
+struct mpt3_enable_diag_sbr_reload {
+	struct mpt3_ioctl_header hdr;
+};
+
 #endif /* MPT3SAS_CTL_H_INCLUDED */
diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
index 51b5788da040..ef8ee93005ea 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
@@ -12240,6 +12240,7 @@  _scsih_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
 	/* misc semaphores and spin locks */
 	mutex_init(&ioc->reset_in_progress_mutex);
+	mutex_init(&ioc->hostdiag_unlock_mutex);
 	/* initializing pci_access_mutex lock */
 	mutex_init(&ioc->pci_access_mutex);
 	spin_lock_init(&ioc->ioc_reset_in_progress_lock);