| Message ID | 20240111110505.1563291-1-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On Thu, 11 Jan 2024 at 11:05, Peter Maydell <peter.maydell@linaro.org> wrote: > > Mostly my FEAT_NV/NV2 stuff, but some other smaller series too. > > -- PMM > > The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac: > > Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2024-01-09 10:32:23 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240111 > > for you to fetch changes up to e2862554c257e908a3833265e38365e794abd362: > > target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs (2024-01-09 14:44:45 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * Emulate FEAT_NV, FEAT_NV2 > * add cache controller for Freescale i.MX6 > * Add minimal support for the B-L475E-IOT01A board > * Allow SoC models to configure M-profile CPUs with correct number > of NVIC priority bits > * Add missing QOM parent for v7-M SoCs > * Set CTR_EL0.{IDC,DIC} for the 'max' CPU > * hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0 for any user-visible changes. -- PMM
Mostly my FEAT_NV/NV2 stuff, but some other smaller series too. -- PMM The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2024-01-09 10:32:23 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240111 for you to fetch changes up to e2862554c257e908a3833265e38365e794abd362: target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs (2024-01-09 14:44:45 +0000) ---------------------------------------------------------------- target-arm queue: * Emulate FEAT_NV, FEAT_NV2 * add cache controller for Freescale i.MX6 * Add minimal support for the B-L475E-IOT01A board * Allow SoC models to configure M-profile CPUs with correct number of NVIC priority bits * Add missing QOM parent for v7-M SoCs * Set CTR_EL0.{IDC,DIC} for the 'max' CPU * hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers ---------------------------------------------------------------- Inès Varhol (2): hw/arm: Add minimal support for the STM32L4x5 SoC hw/arm: Add minimal support for the B-L475E-IOT01A board Nikita Ostrenkov (1): hw/arm: add cache controller for Freescale i.MX6 Peter Maydell (34): target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV target/arm: Implement HCR_EL2.AT handling target/arm: Enable trapping of ERET for FEAT_NV target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set target/arm: Allow use of upper 32 bits of TBFLAG_A64 target/arm: Record correct opcode fields in cpreg for E2H aliases target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0 target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check target/arm: Trap sysreg accesses for FEAT_NV target/arm: Make NV reads of CurrentEL return EL2 target/arm: Set SPSR_EL1.M correctly when nested virt is enabled target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} target/arm: Always use arm_pan_enabled() when checking if PAN is enabled target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 target/arm: Handle FEAT_NV page table attribute changes target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits target/arm: Implement VNCR_EL2 register target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 target/arm: Implement FEAT_NV2 redirection of sysregs to RAM target/arm: Report VNCR_EL2 based faults correctly target/arm: Mark up VNCR offsets (offsets 0x0..0xff) target/arm: Mark up VNCR offsets (offsets 0x100..0x160) target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs Philippe Mathieu-Daudé (1): hw/arm: Add missing QOM parent for v7-M SoCs Samuel Tardieu (3): hw/intc/armv7m_nvic: add "num-prio-bits" property hw/arm/armv7m: alias the NVIC "num-prio-bits" property hw/arm/socs: configure priority bits for existing SOCs MAINTAINERS | 15 ++ docs/system/arm/b-l475e-iot01a.rst | 46 +++++ docs/system/arm/emulation.rst | 2 + docs/system/arm/stm32.rst | 6 +- docs/system/target-arm.rst | 1 + configs/devices/arm-softmmu/default.mak | 1 + include/hw/arm/armv7m.h | 1 + include/hw/arm/stm32l4x5_soc.h | 57 ++++++ target/arm/cpregs.h | 54 +++++- target/arm/cpu-features.h | 10 + target/arm/cpu.h | 24 ++- target/arm/syndrome.h | 20 +- target/arm/tcg/translate.h | 16 +- hw/arm/armv7m.c | 2 + hw/arm/b-l475e-iot01a.c | 72 +++++++ hw/arm/fsl-imx6.c | 3 + hw/arm/msf2-som.c | 1 + hw/arm/netduino2.c | 1 + hw/arm/netduinoplus2.c | 1 + hw/arm/olimex-stm32-h405.c | 1 + hw/arm/stellaris.c | 2 + hw/arm/stm32f100_soc.c | 1 + hw/arm/stm32f205_soc.c | 1 + hw/arm/stm32f405_soc.c | 1 + hw/arm/stm32l4x5_soc.c | 266 ++++++++++++++++++++++++++ hw/arm/stm32vldiscovery.c | 1 + hw/intc/arm_gicv3_cpuif.c | 28 ++- hw/intc/armv7m_nvic.c | 23 ++- target/arm/cpu.c | 8 +- target/arm/debug_helper.c | 13 +- target/arm/helper.c | 326 +++++++++++++++++++++++++++++--- target/arm/ptw.c | 21 ++ target/arm/tcg/cpu64.c | 11 ++ target/arm/tcg/hflags.c | 30 ++- target/arm/tcg/op_helper.c | 16 +- target/arm/tcg/tlb_helper.c | 27 ++- target/arm/tcg/translate-a64.c | 160 ++++++++++++++-- hw/arm/Kconfig | 12 ++ hw/arm/meson.build | 2 + 39 files changed, 1203 insertions(+), 80 deletions(-) create mode 100644 docs/system/arm/b-l475e-iot01a.rst create mode 100644 include/hw/arm/stm32l4x5_soc.h create mode 100644 hw/arm/b-l475e-iot01a.c create mode 100644 hw/arm/stm32l4x5_soc.c