| Message ID | 20240115172007.309547-6-Benjamin.Cheatham@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | CXL, ACPI, APEI, EINJ: Update EINJ for CXL error types | expand |
Ben Cheatham wrote: > Update EINJ kernel document to include how to inject CXL protocol error > types, build the kernel to include CXL error types, and give an example > injection. > > Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com> > --- > .../firmware-guide/acpi/apei/einj.rst | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst > index d6b61d22f525..a8f26845682a 100644 > --- a/Documentation/firmware-guide/acpi/apei/einj.rst > +++ b/Documentation/firmware-guide/acpi/apei/einj.rst > @@ -181,6 +181,25 @@ You should see something like this in dmesg:: > [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 > [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) > > +CXL error types are supported from ACPI 6.5 onwards. These error types > +are not available in the legacy interface at /sys/kernel/debug/apei/einj, > +and are instead at /sys/kernel/debug/cxl/. There is a file under debug/cxl > +called "einj_type" that is analagous to available_error_type under debug/cxl. s/analagous/analogous/ Other than that, looks good.
On 1/16/24 5:57 PM, Dan Williams wrote: > Ben Cheatham wrote: >> Update EINJ kernel document to include how to inject CXL protocol error >> types, build the kernel to include CXL error types, and give an example >> injection. >> >> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com> >> --- >> .../firmware-guide/acpi/apei/einj.rst | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst >> index d6b61d22f525..a8f26845682a 100644 >> --- a/Documentation/firmware-guide/acpi/apei/einj.rst >> +++ b/Documentation/firmware-guide/acpi/apei/einj.rst >> @@ -181,6 +181,25 @@ You should see something like this in dmesg:: >> [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 >> [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) >> >> +CXL error types are supported from ACPI 6.5 onwards. These error types >> +are not available in the legacy interface at /sys/kernel/debug/apei/einj, >> +and are instead at /sys/kernel/debug/cxl/. There is a file under debug/cxl >> +called "einj_type" that is analagous to available_error_type under debug/cxl. > > s/analagous/analogous/ > > Other than that, looks good. Thanks for pointing that out! Thanks, Ben
diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst index d6b61d22f525..a8f26845682a 100644 --- a/Documentation/firmware-guide/acpi/apei/einj.rst +++ b/Documentation/firmware-guide/acpi/apei/einj.rst @@ -181,6 +181,25 @@ You should see something like this in dmesg:: [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) +CXL error types are supported from ACPI 6.5 onwards. These error types +are not available in the legacy interface at /sys/kernel/debug/apei/einj, +and are instead at /sys/kernel/debug/cxl/. There is a file under debug/cxl +called "einj_type" that is analagous to available_error_type under debug/cxl. +There is also a "einj_inject" file in each $dport_dev directory under debug/cxl +that will inject a given error into the dport represented by $dport_dev. +For example, to inject a CXL.mem protocol correctable error into +$dport_dev=pci0000:0c:: + + # cd /sys/kernel/debug/cxl/ + # cat einj_type # See which error can be injected + 0x00008000 CXL.mem Protocol Correctable + 0x00010000 CXL.mem Protocol Uncorrectable non-fatal + 0x00020000 CXL.mem Protocol Uncorrectable fatal + # cd 0000:e0:01.1 # Navigate to dport to inject into + # echo 0x8000 > einj_inject # Inject error + +To use CXL error types, ``CONFIG_CXL_EINJ`` will need to be enabled. + Special notes for injection into SGX enclaves: There may be a separate BIOS setup option to enable SGX injection.
Update EINJ kernel document to include how to inject CXL protocol error types, build the kernel to include CXL error types, and give an example injection. Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com> --- .../firmware-guide/acpi/apei/einj.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)