| Message ID | 20240117173458.2312669-7-quic_sibis@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | firmware: arm_scmi: Qualcomm Vendor Protocol | expand |
(Generic note: It is middle of merge window and I have seen multiple series posted by you. Since I am mainly looking for bug fixes only ATM, I may miss to look at few. You may have to ping or repost after the merge window, just responding to this for now as it caught my attention) On Wed, Jan 17, 2024 at 11:04:57PM +0530, Sibi Sankar wrote: > Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. > > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index afdbd27f8346..6856a206f7fc 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -62,6 +62,7 @@ CPU0: cpu@0 { > compatible = "qcom,oryon"; > reg = <0x0 0x0>; > enable-method = "psci"; > + clocks = <&scmi_dvfs 0>; I would use genpd bindings Ulf added recently. The reason I ask is I remember one of the Qcom platform had both clocks and qcom,freq-domain and each one served different purpose with latter one being used for cpufreq. So will that be an issue here ?
On 1/18/24 20:55, Sudeep Holla wrote: > (Generic note: It is middle of merge window and I have seen multiple > series posted by you. Since I am mainly looking for bug fixes only ATM, > I may miss to look at few. You may have to ping or repost after the merge > window, just responding to this for now as it caught my attention) ack > > On Wed, Jan 17, 2024 at 11:04:57PM +0530, Sibi Sankar wrote: >> Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. >> >> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> index afdbd27f8346..6856a206f7fc 100644 >> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> @@ -62,6 +62,7 @@ CPU0: cpu@0 { >> compatible = "qcom,oryon"; >> reg = <0x0 0x0>; >> enable-method = "psci"; >> + clocks = <&scmi_dvfs 0>; > > I would use genpd bindings Ulf added recently. The reason I ask is I remember > one of the Qcom platform had both clocks and qcom,freq-domain and each one > served different purpose with latter one being used for cpufreq. So will > that be an issue here ? The cpufreq-hw node that Qualcomm used had a opp-table associated with it to vote for various buses which in turn required both clock and freq- domain. However the memory buses voting is done by the vendor protocol 0x80 on X1E and hence won't be an issue here. -Sibi >
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index afdbd27f8346..6856a206f7fc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -62,6 +62,7 @@ CPU0: cpu@0 { compatible = "qcom,oryon"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -79,6 +80,7 @@ CPU1: cpu@100 { compatible = "qcom,oryon"; reg = <0x0 0x100>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -90,6 +92,7 @@ CPU2: cpu@200 { compatible = "qcom,oryon"; reg = <0x0 0x200>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -101,6 +104,7 @@ CPU3: cpu@300 { compatible = "qcom,oryon"; reg = <0x0 0x300>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -112,6 +116,7 @@ CPU4: cpu@10000 { compatible = "qcom,oryon"; reg = <0x0 0x10000>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; @@ -129,6 +134,7 @@ CPU5: cpu@10100 { compatible = "qcom,oryon"; reg = <0x0 0x10100>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; @@ -140,6 +146,7 @@ CPU6: cpu@10200 { compatible = "qcom,oryon"; reg = <0x0 0x10200>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; @@ -151,6 +158,7 @@ CPU7: cpu@10300 { compatible = "qcom,oryon"; reg = <0x0 0x10300>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; @@ -162,6 +170,7 @@ CPU8: cpu@20000 { compatible = "qcom,oryon"; reg = <0x0 0x20000>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD8>; power-domain-names = "psci"; @@ -179,6 +188,7 @@ CPU9: cpu@20100 { compatible = "qcom,oryon"; reg = <0x0 0x20100>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD9>; power-domain-names = "psci"; @@ -190,6 +200,7 @@ CPU10: cpu@20200 { compatible = "qcom,oryon"; reg = <0x0 0x20200>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD10>; power-domain-names = "psci"; @@ -201,6 +212,7 @@ CPU11: cpu@20300 { compatible = "qcom,oryon"; reg = <0x0 0x20300>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD11>; power-domain-names = "psci"; @@ -303,6 +315,21 @@ scm: scm { interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; }; clk_virt: interconnect-0 {
Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)