| Message ID | 20240123063842.35255-5-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/cortex-a: Check for CPU types in machine_run_board_init() | expand |
On 1/23/24 07:38, Philippe Mathieu-Daudé wrote: > Restrict MachineClass::valid_cpu_types[] to the single > valid CPU type. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/arm/aspeed.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index cc59176563..e0e0877b1d 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -1147,6 +1147,11 @@ static int aspeed_soc_num_cpus(const char *soc_name) > return sc->num_cpus; > } > > +static const char * const ast2400_a1_valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("arm926"), > + NULL > +}; > + > static void aspeed_machine_class_init(ObjectClass *oc, void *data) > { > MachineClass *mc = MACHINE_CLASS(oc); > @@ -1175,6 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) > amc->spi_model = "mx25l25635f"; > amc->num_cs = 1; > amc->i2c_init = palmetto_bmc_i2c_init; > + mc->valid_cpu_types = ast2400_a1_valid_cpu_types; > mc->default_ram_size = 256 * MiB; > mc->default_cpus = mc->min_cpus = mc->max_cpus = > aspeed_soc_num_cpus(amc->soc_name); > @@ -1192,6 +1198,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) > amc->spi_model = "mx25l25635e"; > amc->num_cs = 1; > amc->i2c_init = quanta_q71l_bmc_i2c_init; > + mc->valid_cpu_types = ast2400_a1_valid_cpu_types; > mc->default_ram_size = 128 * MiB; > mc->default_cpus = mc->min_cpus = mc->max_cpus = > aspeed_soc_num_cpus(amc->soc_name); > @@ -1211,6 +1218,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, > amc->num_cs = 1; > amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; > amc->i2c_init = palmetto_bmc_i2c_init; > + mc->valid_cpu_types = ast2400_a1_valid_cpu_types; > mc->default_ram_size = 256 * MiB; > } >
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cc59176563..e0e0877b1d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1147,6 +1147,11 @@ static int aspeed_soc_num_cpus(const char *soc_name) return sc->num_cpus; } +static const char * const ast2400_a1_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("arm926"), + NULL +}; + static void aspeed_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1175,6 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) amc->spi_model = "mx25l25635f"; amc->num_cs = 1; amc->i2c_init = palmetto_bmc_i2c_init; + mc->valid_cpu_types = ast2400_a1_valid_cpu_types; mc->default_ram_size = 256 * MiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); @@ -1192,6 +1198,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) amc->spi_model = "mx25l25635e"; amc->num_cs = 1; amc->i2c_init = quanta_q71l_bmc_i2c_init; + mc->valid_cpu_types = ast2400_a1_valid_cpu_types; mc->default_ram_size = 128 * MiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); @@ -1211,6 +1218,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, amc->num_cs = 1; amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init = palmetto_bmc_i2c_init; + mc->valid_cpu_types = ast2400_a1_valid_cpu_types; mc->default_ram_size = 256 * MiB; }
Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/arm/aspeed.c | 8 ++++++++ 1 file changed, 8 insertions(+)