| Message ID | 20240130-b4-qcom-common-target-v3-6-e523cbf9e556@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Qualcomm generic board support | expand |
On Tue, 30 Jan 2024 at 19:35, Caleb Connolly <caleb.connolly@linaro.org> wrote: > > We should be returning the rate that we set the clock to, drivers like > MMC rely on this. So fix it. I suppose following diff make sense on top of this patch given the MMC driver clock changes: diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 03fd65a9328b..97668f18cd8c 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -208,9 +208,6 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); return rate; - case GCC_SDCC1_AHB_CLK: - clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); - break; case GCC_ETH_RGMII_CLK: if (rate == 250000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, @@ -225,9 +222,11 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); return rate; + default: + log_warning("Unknown clock id %ld\n", clk->id); + break; } - log_warning("Unknown clock id %ld\n", clk->id); return 0; } @@ -304,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk) clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, CFG_CLK_SRC_CXO); break; + case GCC_SDCC1_AHB_CLK: + clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); + break; default: return 0; } -Sumit > > Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> > --- > drivers/clk/qcom/clock-qcs404.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c > index f5b352803927..03fd65a9328b 100644 > --- a/drivers/clk/qcom/clock-qcs404.c > +++ b/drivers/clk/qcom/clock-qcs404.c > @@ -207,7 +207,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) > CFG_CLK_SRC_GPLL0, 8); > clk_enable_gpll0(priv->base, &gpll0_vote_clk); > clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); > - break; > + return rate; > case GCC_SDCC1_AHB_CLK: > clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); > break; > @@ -224,11 +224,10 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) > else if (rate == 5000000) > clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, > CFG_CLK_SRC_GPLL1, 8); > - break; > - default: > - return 0; > + return rate; > } > > + log_warning("Unknown clock id %ld\n", clk->id); > return 0; > } > > > -- > 2.43.0 >
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index f5b352803927..03fd65a9328b 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -207,7 +207,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); - break; + return rate; case GCC_SDCC1_AHB_CLK: clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); break; @@ -224,11 +224,10 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); - break; - default: - return 0; + return rate; } + log_warning("Unknown clock id %ld\n", clk->id); return 0; }
We should be returning the rate that we set the clock to, drivers like MMC rely on this. So fix it. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> --- drivers/clk/qcom/clock-qcs404.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)