| Message ID | 1474990196-808-1-git-send-email-bgolaszewski@baylibre.com |
|---|---|
| State | New |
| Headers | show |
+ Sekhar 2016-09-28 13:19 GMT+02:00 Tomi Valkeinen <tomi.valkeinen@ti.com>: > Hi, > > On 27/09/16 18:29, Bartosz Golaszewski wrote: >> Some architectures don't use the common clock framework and don't >> implement all the clk interfaces for every clock. This is the case >> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1. >> >> Trying to set the clock rate for the LCDC clock results in -EINVAL >> being returned. >> >> As a workaround for that: if the call to clk_set_rate() fails, fall >> back to adjusting the clock divider instead. Proper divider value is >> calculated by dividing the current clock rate by the required pixel >> clock rate in HZ. >> >> This code is based on a hack initially developed internally for >> baylibre by Karl Beldan <kbeldan@baylibre.com>. >> >> Tested with a da850-lcdk with an LCD display connected over VGA. >> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [snip] > > If the clock divider path easily creates pixel clocks that are quite far > from the requested ones (which I think it does), I think it would make > sense to have a print here if the final pixel clock is far enough from > the requested one. And that's a valid print for the current code path > too, as it's not clear whether lcdc's input clock can be set to an exact > value. > >> DBG("lcd_clk=%lu, mode clock=%d, div=%u", >> lcd_clk, crtc->mode.clock, clkdiv); >> @@ -664,7 +682,6 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc) >> tilcdc_set(dev, LCDC_CLK_ENABLE_REG, >> LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | >> LCDC_V2_CORE_CLK_EN); >> - Hi Tomi, how far is far enough to emit a warning? On da850 the requested rate is 228000000 Hz, while the calculated divider is 6, which results in the real rate of 225000000 Hz. This is less than 1% difference - should we take this value as reference? I'll apply all other requested changes. Best regards, Bartosz Golaszewski
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 2087689..f2ff3b1 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -636,22 +636,40 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct tilcdc_drm_private *priv = dev->dev_private; unsigned long lcd_clk; - const unsigned clkdiv = 2; /* using a fixed divider of 2 */ + unsigned int clkdiv; int ret; pm_runtime_get_sync(dev->dev); tilcdc_crtc_disable(crtc); + clkdiv = 2; /* first try using a standard divider of 2 */ + /* mode.clock is in KHz, set_rate wants parameter in Hz */ ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); + lcd_clk = clk_get_rate(priv->clk); if (ret < 0) { - dev_err(dev->dev, "failed to set display clock rate to: %d\n", - crtc->mode.clock); - goto out; - } + /* + * If we fail to set the clock rate (some architectures don't + * use the common clock framework yet and may not implement + * all the clk API calls for every clock), try the next best + * thing: adjusting the clock divider, unless clk_get_rate() + * failed as well. + */ + dev_err(dev->dev, + "failed to set display clock rate to: %d\n", + crtc->mode.clock); + if (!lcd_clk) { + /* Nothing more we can do. Just bail out. */ + dev_err(dev->dev, + "failed to read the display clock rate\n"); + goto out; + } - lcd_clk = clk_get_rate(priv->clk); + dev_info(dev->dev, + "falling back to adjusting the clock divisor\n"); + clkdiv = DIV_ROUND_CLOSEST(lcd_clk, (crtc->mode.clock * 1000)); + } DBG("lcd_clk=%lu, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, clkdiv); @@ -664,7 +682,6 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc) tilcdc_set(dev, LCDC_CLK_ENABLE_REG, LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | LCDC_V2_CORE_CLK_EN); - if (tilcdc_crtc_is_on(crtc)) tilcdc_crtc_enable(crtc);
Some architectures don't use the common clock framework and don't implement all the clk interfaces for every clock. This is the case for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1. Trying to set the clock rate for the LCDC clock results in -EINVAL being returned. As a workaround for that: if the call to clk_set_rate() fails, fall back to adjusting the clock divider instead. Proper divider value is calculated by dividing the current clock rate by the required pixel clock rate in HZ. This code is based on a hack initially developed internally for baylibre by Karl Beldan <kbeldan@baylibre.com>. Tested with a da850-lcdk with an LCD display connected over VGA. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-)