| Message ID | 20240207170425.478558-2-enachman@marvell.com |
|---|---|
| State | New |
| Headers | show |
| Series | Fix PHY init timeout issues | expand |
On Wed, 7 Feb 2024 at 18:04, Elad Nachman <enachman@marvell.com> wrote: > > From: Elad Nachman <enachman@marvell.com> > > Each time SD/mmc phy is initialized, at times, in some of > the attempts, phy fails to completes its initialization > which results into timeout error. Per the HW spec, it is > a pre-requisite to ensure a stable SD clock before a phy > initialization is attempted. > > Signed-off-by: Elad Nachman <enachman@marvell.com> > --- > drivers/mmc/host/sdhci-xenon-phy.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c > index 8cf3a375de65..4e99197b62c3 100644 > --- a/drivers/mmc/host/sdhci-xenon-phy.c > +++ b/drivers/mmc/host/sdhci-xenon-phy.c > @@ -216,6 +216,24 @@ static int xenon_alloc_emmc_phy(struct sdhci_host *host) > return 0; > } > > +static int xenon_check_stability_internal_clk(struct sdhci_host *host) > +{ > + u32 reg; > + ktime_t timeout; > + > + /* Wait max 20 ms */ > + timeout = ktime_add_ms(ktime_get(), 20); > + while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) > + & SDHCI_CLOCK_INT_STABLE)) { > + if (ktime_after(ktime_get(), timeout)) { > + dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n"); > + return -ETIMEDOUT; > + } > + usleep_range(900, 1100); > + } > + return 0; Please convert the above into readx_poll_timeout() or similar. > +} > + > /* > * eMMC 5.0/5.1 PHY init/re-init. > * eMMC PHY init should be executed after: > @@ -232,6 +250,11 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) > struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); > struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; > > + int ret = xenon_check_stability_internal_clk(host); > + > + if (ret) > + return ret; > + > reg = sdhci_readl(host, phy_regs->timing_adj); > reg |= XENON_PHY_INITIALIZAION; > sdhci_writel(host, reg, phy_regs->timing_adj); Kind regards Uffe
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index 8cf3a375de65..4e99197b62c3 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -216,6 +216,24 @@ static int xenon_alloc_emmc_phy(struct sdhci_host *host) return 0; } +static int xenon_check_stability_internal_clk(struct sdhci_host *host) +{ + u32 reg; + ktime_t timeout; + + /* Wait max 20 ms */ + timeout = ktime_add_ms(ktime_get(), 20); + while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n"); + return -ETIMEDOUT; + } + usleep_range(900, 1100); + } + return 0; +} + /* * eMMC 5.0/5.1 PHY init/re-init. * eMMC PHY init should be executed after: @@ -232,6 +250,11 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; + int ret = xenon_check_stability_internal_clk(host); + + if (ret) + return ret; + reg = sdhci_readl(host, phy_regs->timing_adj); reg |= XENON_PHY_INITIALIZAION; sdhci_writel(host, reg, phy_regs->timing_adj);