| Message ID | 20240209085347.8446-1-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [dubious,RFC] target/mips: Allow I6500 CPU to access CP0 SAAR registers | expand |
On 9/2/24 09:53, Philippe Mathieu-Daudé wrote: > Desperate attempt to enable access from ITU to SAAR registers, by > taking missing part of commits c9340491cc ("target-mips: implement > SAARI/SAAR registers") and c1af807054 ("target-mips: add I6500 core > configuration") from [*] which were partly committed as 5fb2dcd179 > ("target/mips: Provide R/W access to SAARI and SAAR CP0 registers"). > > [*] https://github.com/MIPS/qemu/commit/c9340491cc. > > Reported-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > I can not test this. We don't test the I6500 anyway. Besides this > CPU lacks DSPRAM support which was never merged, see: > https://lore.kernel.org/qemu-devel/1566216496-17375-2-git-send-email-aleksandar.markovic@rt-rk.com/ > and: > https://github.com/MIPS/qemu/commit/a4c1477c84#diff-5362bb61a4a73490270458b19e452bac9b3b907f4efd59ece6494ec19d033a81 > so I doubt it is really useful in its current incomplete state. > --- > target/mips/cpu.c | 1 + > target/mips/tcg/translate.c | 1 + > target/mips/cpu-defs.c.inc | 1 + > 3 files changed, 3 insertions(+) Patch discarded in favor of: https://lore.kernel.org/qemu-devel/20240209090513.9401-1-philmd@linaro.org/
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d644adbc77..6fa5902ec7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -256,6 +256,7 @@ static void mips_cpu_reset_hold(Object *obj) env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; env->msair = env->cpu_model->MSAIR; env->insn_flags = env->cpu_model->insn_flags; + env->saarp = env->cpu_model->SAARP; #if defined(CONFIG_USER_ONLY) env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 12094cc1e7..ee2b4051f3 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15405,6 +15405,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; + ctx->saar = (bool) env->saarp; ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fbf787d8ce..6885196dca 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -817,6 +817,7 @@ const mips_def_t mips_defs[] = .PABITS = 48, .insn_flags = CPU_MIPS64R6, .mmu_type = MMU_TYPE_R4000, + .SAARP = 1, }, { .name = "Loongson-2E",
Desperate attempt to enable access from ITU to SAAR registers, by taking missing part of commits c9340491cc ("target-mips: implement SAARI/SAAR registers") and c1af807054 ("target-mips: add I6500 core configuration") from [*] which were partly committed as 5fb2dcd179 ("target/mips: Provide R/W access to SAARI and SAAR CP0 registers"). [*] https://github.com/MIPS/qemu/commit/c9340491cc. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- I can not test this. We don't test the I6500 anyway. Besides this CPU lacks DSPRAM support which was never merged, see: https://lore.kernel.org/qemu-devel/1566216496-17375-2-git-send-email-aleksandar.markovic@rt-rk.com/ and: https://github.com/MIPS/qemu/commit/a4c1477c84#diff-5362bb61a4a73490270458b19e452bac9b3b907f4efd59ece6494ec19d033a81 so I doubt it is really useful in its current incomplete state. --- target/mips/cpu.c | 1 + target/mips/tcg/translate.c | 1 + target/mips/cpu-defs.c.inc | 1 + 3 files changed, 3 insertions(+)