| Message ID | 20240206135115.151218-3-biju.das.jz@bp.renesas.com |
|---|---|
| State | Accepted |
| Commit | d3c49299339051b17ae3f2fe70fa5af7bbb82011 |
| Headers | show |
| Series | [v2,1/3] pinctrl: renesas: rzg2l: Configure interrupt input mode | expand |
Hi Biju, On Tue, Feb 6, 2024 at 2:51 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Simplify rzg2l_gpio_irq_{en,dis}able by adding a helper function > rzg2l_gpio_irq_endisable(). > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v2: > * New patch Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Note that this conflicts with Prabhakar's "[PATCH 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC" https://lore.kernel.org/all/20240129151618.90922-3-prabhakar.mahadev-lad.rj@bp.renesas.com Gr{oetje,eeting}s, Geert
Hi Geert, Thanks for the feedback. On Mon, Feb 12, 2024 at 3:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Biju, > > On Tue, Feb 6, 2024 at 2:51 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Simplify rzg2l_gpio_irq_{en,dis}able by adding a helper function > > rzg2l_gpio_irq_endisable(). > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v2: > > * New patch > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Note that this conflicts with Prabhakar's "[PATCH 2/5] > irqchip/renesas-rzg2l: Add support for RZ/Five SoC" > https://lore.kernel.org/all/20240129151618.90922-3-prabhakar.mahadev-lad.rj@bp.renesas.com Do you mean patch [1] conflicts with the above as it is irqchip related? [1] https://lore.kernel.org/all/20240212113712.71878-6-biju.das.jz@bp.renesas.com/ Cheers, Biju
Hi Biju, On Mon, Feb 12, 2024 at 6:03 PM Biju Das <biju.das.au@gmail.com> wrote: > On Mon, Feb 12, 2024 at 3:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Tue, Feb 6, 2024 at 2:51 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > Simplify rzg2l_gpio_irq_{en,dis}able by adding a helper function > > > rzg2l_gpio_irq_endisable(). > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > > --- > > > v2: > > > * New patch > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > Note that this conflicts with Prabhakar's "[PATCH 2/5] > > irqchip/renesas-rzg2l: Add support for RZ/Five SoC" > > https://lore.kernel.org/all/20240129151618.90922-3-prabhakar.mahadev-lad.rj@bp.renesas.com > > Do you mean patch [1] conflicts with the above as it is irqchip related? > [1] > https://lore.kernel.org/all/20240212113712.71878-6-biju.das.jz@bp.renesas.com/ Oops, you're right. I've been seeing too many patches today... Gr{oetje,eeting}s, Geert
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 03725a3c6703..d400dcb048fc 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1809,11 +1809,9 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl return gpioint; } -static void rzg2l_gpio_irq_disable(struct irq_data *d) +static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, + unsigned int hwirq, bool enable) { - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); - unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); @@ -1821,8 +1819,6 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) unsigned long flags; void __iomem *addr; - irq_chip_disable_parent(d); - addr = pctrl->base + ISEL(off); if (bit >= 4) { bit -= 4; @@ -1830,9 +1826,21 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) } spin_lock_irqsave(&pctrl->lock, flags); - writel(readl(addr) & ~BIT(bit * 8), addr); + if (enable) + writel(readl(addr) | BIT(bit * 8), addr); + else + writel(readl(addr) & ~BIT(bit * 8), addr); spin_unlock_irqrestore(&pctrl->lock, flags); +} +static void rzg2l_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + unsigned int hwirq = irqd_to_hwirq(d); + + irq_chip_disable_parent(d); + rzg2l_gpio_irq_endisable(pctrl, hwirq, false); gpiochip_disable_irq(gc, hwirq); } @@ -1841,25 +1849,9 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); - const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - u64 *pin_data = pin_desc->drv_data; - u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); - u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); - unsigned long flags; - void __iomem *addr; gpiochip_enable_irq(gc, hwirq); - - addr = pctrl->base + ISEL(off); - if (bit >= 4) { - bit -= 4; - addr += 4; - } - - spin_lock_irqsave(&pctrl->lock, flags); - writel(readl(addr) | BIT(bit * 8), addr); - spin_unlock_irqrestore(&pctrl->lock, flags); - + rzg2l_gpio_irq_endisable(pctrl, hwirq, true); irq_chip_enable_parent(d); }
Simplify rzg2l_gpio_irq_{en,dis}able by adding a helper function rzg2l_gpio_irq_endisable(). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v2: * New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 40 ++++++++++--------------- 1 file changed, 16 insertions(+), 24 deletions(-)