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[54.225.227.206]) by mx.google.com with ESMTP id p29si5270630qta.7.2016.10.12.19.05.35; Wed, 12 Oct 2016 19:05:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 87A146174D; Thu, 13 Oct 2016 02:05:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 7C26B6175E; Thu, 13 Oct 2016 02:01:43 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 582CE61745; Thu, 13 Oct 2016 02:01:30 +0000 (UTC) Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by lists.linaro.org (Postfix) with ESMTPS id 944186174E for ; Thu, 13 Oct 2016 02:00:50 +0000 (UTC) Received: by mail-pf0-f182.google.com with SMTP id e6so26836656pfk.3 for ; Wed, 12 Oct 2016 19:00:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qJWrzHpn98LAXpfvmpqL51ei8ehqu7mSCT0TOjLrXBE=; b=PFfDH7rxXz5Rt9+3tQAvFo0HNnVYqckNja6d0MDkYHGxs93WDPiftS+/ez7zDL/6oB 58b+TAQoG5i/NtUZmRi2hqX7hGwr6DtnnHG22EFg9eJCcxf00KQibwtS5XM5oWIhyHKQ 4kV3WYDxrvclqr0NAYNKOfrA2ooWOLF0Tv1XJDUpE7Z0B/x4FF4/laeaFAjezjVWq+76 AYezXq9tSfepA+O+amj5jhtJilPs6D2bC7OG9y3RVHiFHhTWAiLDlvPiAkty3f7U3KZF 0IaXfsat+fDy6yDdemz0w12bHEzGDBcXMId5fujP/aSaU6F1fmwm3wOYBpMpiVHedlNN 6lFQ== X-Gm-Message-State: AA6/9Rk+mKK8koWByaWmbDSAc3ZXqF/cU+ICb1L3Lo9OatohTCScegXvMXhAl/VHsBPwrg+yKXA= X-Received: by 10.98.149.149 with SMTP id c21mr6436069pfk.100.1476324049885; Wed, 12 Oct 2016 19:00:49 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id sv8sm14732756pab.18.2016.10.12.19.00.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 12 Oct 2016 19:00:49 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 13 Oct 2016 10:00:17 +0800 Message-Id: <1476324020-57155-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476324020-57155-1-git-send-email-heyi.guo@linaro.org> References: <1476324020-57155-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 08/11] Hisilicon: Update some headers file to support Hi1616 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 60 +++++++++++++++++++--- .../Hisilicon/Include/Library/PlatformSysCtrlLib.h | 6 +++ Chips/Hisilicon/Include/PlatformArch.h | 2 + 3 files changed, 60 insertions(+), 8 deletions(-) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index f424ae9..09aef56 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -123,8 +123,8 @@ typedef struct _DDR_DIMM{ UINT8 MtbDividend; UINT8 MtbDivsor; UINT8 nCL; - UINT8 nRCD; - UINT8 nRP; + UINT32 nRCD; + UINT32 nRP; UINT8 SPDftb; UINT8 SpdMinTCK; UINT8 SpdMinTCKFtb; @@ -173,8 +173,14 @@ typedef struct { UINT32 ddrcTiming5; UINT32 ddrcTiming6; UINT32 ddrcTiming7; + UINT32 ddrcTiming8; }DDRC_TIMING; +typedef struct _MARGIN_RESULT{ + UINT32 OptimalDramVref[12]; + UINT32 optimalPhyVref[18]; +}MARGIN_RESULT; + typedef struct _DDR_Channel{ BOOLEAN Status; UINT8 CurrentDimmNum; @@ -184,22 +190,42 @@ typedef struct _DDR_Channel{ UINT8 DramWidth; UINT8 ModuleType; UINT32 MemSize; + UINT32 tck; + UINT32 ratio; UINT32 CLSupport; UINT32 minTck; + UINT32 taref; + UINT32 nAA; + UINT32 nAOND; + UINT32 nCKE; UINT32 nCL; - UINT32 nWR; + UINT32 nCCDL; + UINT32 nCKSRX; + UINT32 nCKSRE; + UINT32 nCCDNSW; + UINT32 nCCDNSR; + UINT32 nFAW; + UINT32 nMRD; + UINT32 nMOD; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC; - UINT32 nWTR; + UINT32 nRFCAB; UINT32 nRTP; - UINT32 nAA; - UINT32 nFAW; + UINT32 nRTW; UINT32 nRP; - UINT32 nCCDL; + UINT32 nSRE; + UINT32 nWL; + UINT32 nWR; + UINT32 nWTR; + UINT32 nWTRL; + UINT32 nXARD; + UINT32 nZQPRD; + UINT32 nZQINIT; + UINT32 nZQCS; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en; @@ -228,15 +254,23 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig; - UINT32 phyDqsFailRiseDelay; + UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency; + UINT32 dimm_parity_en; DDRC_TIMING ddrcTiming; DDR_DIMM Dimm[MAX_DIMM]; + MARGIN_RESULT sMargin; }DDR_CHANNEL; typedef struct _NVRAM_RANK{ + UINT16 MR0; + UINT16 MR1; + UINT16 MR2; + UINT16 MR3; + UINT16 MR4; + UINT16 MR5; UINT16 MR6[9]; }NVRAM_RANK; @@ -306,6 +340,14 @@ typedef struct _MEMORY{ UINT32 Config2; }MEMORY; +typedef struct _NUMAINFO{ + UINT8 NodeId; + UINT64 Base; + UINT64 Length; + UINT32 DieInterleaveEn; +}NUMAINFO; + + typedef struct _GBL_DATA { DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL]; @@ -319,6 +361,7 @@ typedef struct _GBL_DATA UINT32 SpdTck; UINT32 Tck; UINT32 DdrFreqIdx; + UINT32 DevParaFreqIdx; UINT32 MemSize; UINT32 EccEn; @@ -365,6 +408,7 @@ typedef struct _GBL_DATA BOOLEAN chipIsEc; NVRAM nvram; MEMORY mem; + NUMAINFO NumaInfo[MAX_NODE_TYPE][MAX_NUM_PER_TYPE]; }GBL_DATA, *pGBL_DATA; diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h index f374112..23e1393 100644 --- a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h @@ -90,8 +90,14 @@ VOID DResetUsb (); UINT32 PlatformGetEhciBase (); UINT32 PlatformGetOhciBase (); VOID PlatformPllInit(); +VOID SiclPllInit(UINT32 SclId); VOID PlatformDeviceDReset(); VOID PlatformGicdInit(); VOID PlatformLpcInit(); +VOID PlatformArchTimerSynchronize(); +VOID PlatformEventBroadcastConfig(); +UINTN GetDjtagRegBase(UINT32 NodeId); +VOID LlcCleanInvalidateAsm(); +VOID PlatformMdioInit(); #endif diff --git a/Chips/Hisilicon/Include/PlatformArch.h b/Chips/Hisilicon/Include/PlatformArch.h index f1ccbb6..b34f62f 100644 --- a/Chips/Hisilicon/Include/PlatformArch.h +++ b/Chips/Hisilicon/Include/PlatformArch.h @@ -26,6 +26,8 @@ #define MAX_DIMM 3 #define MAX_RANK_CH 12 #define MAX_RANK_DIMM 4 +#define MAX_NODE_TYPE 4 +#define MAX_NUM_PER_TYPE 8 #define S1_BASE 0x40000000000