| Message ID | 20240228085613.3935476-1-jisheng.teoh@starfivetech.com |
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Wed, 28 Feb 2024 08:58:36 +0000 From: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> To: Andi Shyti <andi.shyti@kernel.org> Cc: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>, Ley Foon Tan <leyfoon.tan@starfivetech.com>, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Eng Lee Teh <englee.teh@starfivetech.com> Subject: [PATCH] i2c: cadence: Add RISCV architecture support Date: Wed, 28 Feb 2024 16:56:13 +0800 Message-ID: <20240228085613.3935476-1-jisheng.teoh@starfivetech.com> X-Mailer: git-send-email 2.43.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1160.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::6) Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: <linux-i2c.vger.kernel.org> List-Subscribe: <mailto:linux-i2c+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-i2c+unsubscribe@vger.kernel.org> MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1160:EE_|ZQ0PR01MB1158:EE_ X-MS-Office365-Filtering-Correlation-Id: c6c8eac7-3e79-4308-6228-08dc383b730a X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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i2c: cadence: Add RISCV architecture support
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diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 28eb48dd5b32..0f47413ce7b7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -500,7 +500,7 @@ config I2C_BRCMSTB config I2C_CADENCE tristate "Cadence I2C Controller" - depends on ARCH_ZYNQ || ARM64 || XTENSA || COMPILE_TEST + depends on ARCH_ZYNQ || ARM64 || XTENSA || RISCV || COMPILE_TEST help Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq.