diff mbox series

[v2,1/4] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency

Message ID 20240306140306.876188-2-amadeus@jmu.edu.cn
State Superseded
Headers show
Series arm64: dts: qcom: ipq6018: rework CPU Frequency | expand

Commit Message

Chukun Pan March 6, 2024, 2:03 p.m. UTC
Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,
so add this frequency.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Konrad Dybcio March 6, 2024, 4:20 p.m. UTC | #1
On 3/6/24 15:03, Chukun Pan wrote:
> Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,

(which ones specifically?)

Konrad
> so add this frequency.
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 4e29adea570a..7fdb119083a2 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -119,6 +119,13 @@ opp-1056000000 {
>   			clock-latency-ns = <200000>;
>   		};
>   
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <850000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <200000>;
> +		};

Looks like said SoC can *only* run the CPUs at 1.2 GHz?

Konrad
Robert Marko March 6, 2024, 8:38 p.m. UTC | #2
On 06. 03. 2024. 15:03, Chukun Pan wrote:
> Some IPQ6000 SoCs have CPU frequencies up to 1.2GHz,
> so add this frequency.
>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 4e29adea570a..7fdb119083a2 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -119,6 +119,13 @@ opp-1056000000 {
>   			clock-latency-ns = <200000>;
>   		};
>   
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <850000>;
Can I ask the source of this voltage level?
Because, its not present in the downstream QCA tree at all.

Regards,
Robert
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <200000>;
> +		};
> +
>   		opp-1320000000 {
>   			opp-hz = /bits/ 64 <1320000000>;
>   			opp-microvolt = <862500>;
Robert Marko March 8, 2024, 8:51 a.m. UTC | #3
On Thu, 7 Mar 2024 at 04:26, Chukun Pan <amadeus@jmu.edu.cn> wrote:
>
> Hi, Robert
> > Can I ask the source of this voltage level?
> > Because, its not present in the downstream QCA tree at all.
>
> This voltage level is what I guessed through the mhz tool.
> The downstream QCA tree uses 0.8625v voltage corresponding
> to 1.32GHz, which does not need to be so high.

Well, I am not so sure that it will work for every piece of silicon out there.
In OpenWrt we got bit by fixed voltages on IPQ8074 and had to move to the
downstream CPR driver as the variations between the same family are quite big.

Regards,
Robert
>
> Thanks,
> Chukun
>
> --
> 2.25.1
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 4e29adea570a..7fdb119083a2 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -119,6 +119,13 @@  opp-1056000000 {
 			clock-latency-ns = <200000>;
 		};
 
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <850000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <200000>;
+		};
+
 		opp-1320000000 {
 			opp-hz = /bits/ 64 <1320000000>;
 			opp-microvolt = <862500>;