diff mbox series

[04/15] tcg/i386: Do not accept immediate operand for andc

Message ID 20240312143839.136408-5-richard.henderson@linaro.org
State New
Headers show
Series tcg: Canonicalize operations during optimize | expand

Commit Message

Richard Henderson March 12, 2024, 2:38 p.m. UTC 
The transformation of andc with immediate to and is now
done generically and need not be handled by the backend.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target-con-set.h |  3 +--
 tcg/i386/tcg-target-con-str.h |  1 -
 tcg/i386/tcg-target.c.inc     | 20 +++++---------------
 3 files changed, 6 insertions(+), 18 deletions(-)
diff mbox series

Patch

diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
index e24241cfa2..69d2d38570 100644
--- a/tcg/i386/tcg-target-con-set.h
+++ b/tcg/i386/tcg-target-con-set.h
@@ -40,11 +40,10 @@  C_O1_I2(r, 0, r)
 C_O1_I2(r, 0, re)
 C_O1_I2(r, 0, reZ)
 C_O1_I2(r, 0, ri)
-C_O1_I2(r, 0, rI)
 C_O1_I2(r, L, L)
+C_O1_I2(r, r, r)
 C_O1_I2(r, r, re)
 C_O1_I2(r, r, ri)
-C_O1_I2(r, r, rI)
 C_O1_I2(x, x, x)
 C_N1_I2(r, r, r)
 C_N1_I2(r, r, rW)
diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
index cc22db227b..0c766eac7e 100644
--- a/tcg/i386/tcg-target-con-str.h
+++ b/tcg/i386/tcg-target-con-str.h
@@ -27,7 +27,6 @@  REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)    /* qemu_st8_i32 data */
  * CONST(letter, TCG_CT_CONST_* bit set)
  */
 CONST('e', TCG_CT_CONST_S32)
-CONST('I', TCG_CT_CONST_I32)
 CONST('T', TCG_CT_CONST_TST)
 CONST('W', TCG_CT_CONST_WSZ)
 CONST('Z', TCG_CT_CONST_U32)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index c6ba498623..ed70524864 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -130,9 +130,8 @@  static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
 /* Constants we accept.  */
 #define TCG_CT_CONST_S32 0x100
 #define TCG_CT_CONST_U32 0x200
-#define TCG_CT_CONST_I32 0x400
-#define TCG_CT_CONST_WSZ 0x800
-#define TCG_CT_CONST_TST 0x1000
+#define TCG_CT_CONST_WSZ 0x400
+#define TCG_CT_CONST_TST 0x800
 
 /* Registers used with L constraint, which are the first argument
    registers on x86_64, and two random call clobbered registers on
@@ -203,8 +202,7 @@  static bool tcg_target_const_match(int64_t val, int ct,
         return 1;
     }
     if (type == TCG_TYPE_I32) {
-        if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 |
-                  TCG_CT_CONST_I32 | TCG_CT_CONST_TST)) {
+        if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_TST)) {
             return 1;
         }
     } else {
@@ -214,9 +212,6 @@  static bool tcg_target_const_match(int64_t val, int ct,
         if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
             return 1;
         }
-        if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
-            return 1;
-        }
         /*
          * This will be used in combination with TCG_CT_CONST_S32,
          * so "normal" TESTQ is already matched.  Also accept:
@@ -2666,12 +2661,7 @@  static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         break;
 
     OP_32_64(andc):
-        if (const_a2) {
-            tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
-            tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0);
-        } else {
-            tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
-        }
+        tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
         break;
 
     OP_32_64(mul):
@@ -3442,7 +3432,7 @@  static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 
     case INDEX_op_andc_i32:
     case INDEX_op_andc_i64:
-        return C_O1_I2(r, r, rI);
+        return C_O1_I2(r, r, r);
 
     case INDEX_op_shl_i32:
     case INDEX_op_shl_i64: