diff mbox series

[v2,5/8] clk: qcom: gcc-sc7280: Update force mem core bit for UFS ICE clock

Message ID 20240318053555.20405-6-quic_tdas@quicinc.com
State New
Headers show
Series [v2,1/8] dt-bindings: clock: qcom: Add compatible for QCM6490 boards | expand

Commit Message

Taniya Das March 18, 2024, 5:35 a.m. UTC
Update the force mem core bit for UFS ICE clock to force the core on signal
to remain active during halt state of the clk.

Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 drivers/clk/qcom/gcc-sc7280.c | 3 +++
 1 file changed, 3 insertions(+)

--
2.17.1
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index c622cd9a9d24..b937d513b814 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -3473,6 +3473,9 @@  static int gcc_sc7280_probe(struct platform_device *pdev)
 	qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */
 	regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));

+	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
+	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+
 	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
 			ARRAY_SIZE(gcc_dfs_clocks));
 	if (ret)