| Message ID | 20240319154258.71206-9-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler | expand |
> -----Original Message----- > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Sent: Tuesday, March 19, 2024 10:43 AM > To: qemu-devel@nongnu.org > Cc: qemu-s390x@nongnu.org; Richard Henderson > <richard.henderson@linaro.org>; qemu-ppc@nongnu.org; qemu- > arm@nongnu.org; qemu-riscv@nongnu.org; Anton Johansson <anjo@rev.ng>; > Philippe Mathieu-Daudé <philmd@linaro.org>; Brian Cain > <bcain@quicinc.com> > Subject: [PATCH-for-9.1 08/27] target/hexagon: Convert to > TCGCPUOps::get_cpu_state() > > WARNING: This email originated from outside of Qualcomm. Please be wary > of any links or attachments, and do not enable macros. > > Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state(). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <bcain@quicinc.com> > --- > target/hexagon/cpu.h | 14 -------------- > target/hexagon/cpu.c | 13 +++++++++++++ > 2 files changed, 13 insertions(+), 14 deletions(-) > > diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h > index 935a9c3276..1d42c33827 100644 > --- a/target/hexagon/cpu.h > +++ b/target/hexagon/cpu.h > @@ -134,20 +134,6 @@ struct ArchCPU { > > FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) > > -#define TARGET_HAS_CPU_GET_TB_CPU_STATE > - > -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, > - uint64_t *cs_base, uint32_t *flags) > -{ > - uint32_t hex_flags = 0; > - *pc = env->gpr[HEX_REG_PC]; > - *cs_base = 0; > - if (*pc == env->gpr[HEX_REG_SA0]) { > - hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); > - } > - *flags = hex_flags; > -} > - > typedef HexagonCPU ArchCPU; > > void hexagon_translate_init(void); > diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c > index 3a716b9be3..5e0a9441f2 100644 > --- a/target/hexagon/cpu.c > +++ b/target/hexagon/cpu.c > @@ -273,6 +273,18 @@ static void hexagon_restore_state_to_opc(CPUState > *cs, > cpu_env(cs)->gpr[HEX_REG_PC] = data[0]; > } > > +static void hexagon_get_cpu_state(CPUHexagonState *env, vaddr *pc, > + uint64_t *cs_base, uint32_t *flags) > +{ > + uint32_t hex_flags = 0; > + *pc = env->gpr[HEX_REG_PC]; > + *cs_base = 0; > + if (*pc == env->gpr[HEX_REG_SA0]) { > + hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); > + } > + *flags = hex_flags; > +} > + > static void hexagon_cpu_reset_hold(Object *obj) > { > CPUState *cs = CPU(obj); > @@ -327,6 +339,7 @@ static const TCGCPUOps hexagon_tcg_ops = { > .initialize = hexagon_translate_init, > .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, > .restore_state_to_opc = hexagon_restore_state_to_opc, > + .get_cpu_state = hexagon_get_cpu_state, > }; > > static void hexagon_cpu_class_init(ObjectClass *c, void *data) > -- > 2.41.0
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 935a9c3276..1d42c33827 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -134,20 +134,6 @@ struct ArchCPU { FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) -#define TARGET_HAS_CPU_GET_TB_CPU_STATE - -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags = 0; - *pc = env->gpr[HEX_REG_PC]; - *cs_base = 0; - if (*pc == env->gpr[HEX_REG_SA0]) { - hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags = hex_flags; -} - typedef HexagonCPU ArchCPU; void hexagon_translate_init(void); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3a716b9be3..5e0a9441f2 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -273,6 +273,18 @@ static void hexagon_restore_state_to_opc(CPUState *cs, cpu_env(cs)->gpr[HEX_REG_PC] = data[0]; } +static void hexagon_get_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags = 0; + *pc = env->gpr[HEX_REG_PC]; + *cs_base = 0; + if (*pc == env->gpr[HEX_REG_SA0]) { + hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags = hex_flags; +} + static void hexagon_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); @@ -327,6 +339,7 @@ static const TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, + .get_cpu_state = hexagon_get_cpu_state, }; static void hexagon_cpu_class_init(ObjectClass *c, void *data)
Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/hexagon/cpu.h | 14 -------------- target/hexagon/cpu.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 14 deletions(-)