| Message ID | 20240327214831.1544595-3-helgaas@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | mmc: sdhci-pci-gli: Remove unnecessary device-dependent code | expand |
On Thu, Mar 28, 2024 at 5:49 AM Bjorn Helgaas <helgaas@kernel.org> wrote: > > From: Bjorn Helgaas <bhelgaas@google.com> > > d7133797e9e1 ("mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter > ASPM L1.2") and 36ed2fd32b2c ("mmc: sdhci-pci-gli: A workaround to allow > GL9755 to enter ASPM L1.2") added writes to the Control register in the > Power Management Capability to put the device in D3hot and back to D0. > > Use the pci_set_power_state() interface instead because these are generic > operations that don't need to be driver-specific. Also, the PCI spec > requires some delays after these power transitions, and > pci_set_power_state() takes care of those, while d7133797e9e1 and > 36ed2fd32b2c did not. > > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Hi Bjorn, Thanks. It looks better than the vendor specific. Best regards, Ben Chuang > --- > drivers/mmc/host/sdhci-pci-gli.c | 20 ++++---------------- > 1 file changed, 4 insertions(+), 16 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > index 3d5543581537..0f81586a19df 100644 > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -25,9 +25,6 @@ > #define GLI_9750_WT_EN_ON 0x1 > #define GLI_9750_WT_EN_OFF 0x0 > > -#define PCI_GLI_9750_PM_CTRL 0xFC > -#define PCI_GLI_9750_PM_STATE GENMASK(1, 0) > - > #define SDHCI_GLI_9750_CFG2 0x848 > #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) > #define GLI_9750_CFG2_L1DLY_VALUE 0x1F > @@ -149,9 +146,6 @@ > #define PCI_GLI_9755_MISC 0x78 > #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) > > -#define PCI_GLI_9755_PM_CTRL 0xFC > -#define PCI_GLI_9755_PM_STATE GENMASK(1, 0) > - > #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 > #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) > > @@ -556,11 +550,8 @@ static void gl9750_hw_setting(struct sdhci_host *host) > sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); > > /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ > - pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value); > - value |= PCI_GLI_9750_PM_STATE; > - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); > - value &= ~PCI_GLI_9750_PM_STATE; > - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); > + pci_set_power_state(pdev, PCI_D3hot); > + pci_set_power_state(pdev, PCI_D0); > > /* mask the replay timer timeout of AER */ > aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); > @@ -774,11 +765,8 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) > pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); > > /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ > - pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); > - value |= PCI_GLI_9755_PM_STATE; > - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); > - value &= ~PCI_GLI_9755_PM_STATE; > - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); > + pci_set_power_state(pdev, PCI_D3hot); > + pci_set_power_state(pdev, PCI_D0); > > /* mask the replay timer timeout of AER */ > aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); > -- > 2.34.1 > >
On Thu, 28 Mar 2024 at 02:01, Ben Chuang <benchuanggli@gmail.com> wrote: > > On Thu, Mar 28, 2024 at 5:49 AM Bjorn Helgaas <helgaas@kernel.org> wrote: > > > > From: Bjorn Helgaas <bhelgaas@google.com> > > > > d7133797e9e1 ("mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter > > ASPM L1.2") and 36ed2fd32b2c ("mmc: sdhci-pci-gli: A workaround to allow > > GL9755 to enter ASPM L1.2") added writes to the Control register in the > > Power Management Capability to put the device in D3hot and back to D0. > > > > Use the pci_set_power_state() interface instead because these are generic > > operations that don't need to be driver-specific. Also, the PCI spec > > requires some delays after these power transitions, and > > pci_set_power_state() takes care of those, while d7133797e9e1 and > > 36ed2fd32b2c did not. > > > > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> > > Hi Bjorn, > > Thanks. It looks better than the vendor specific. > > Best regards, > Ben Chuang Hi Ben, I assume I can consider your reply as a reviewed-by tag. If not, please let me know. Kind regards Uffe > > > --- > > drivers/mmc/host/sdhci-pci-gli.c | 20 ++++---------------- > > 1 file changed, 4 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > > index 3d5543581537..0f81586a19df 100644 > > --- a/drivers/mmc/host/sdhci-pci-gli.c > > +++ b/drivers/mmc/host/sdhci-pci-gli.c > > @@ -25,9 +25,6 @@ > > #define GLI_9750_WT_EN_ON 0x1 > > #define GLI_9750_WT_EN_OFF 0x0 > > > > -#define PCI_GLI_9750_PM_CTRL 0xFC > > -#define PCI_GLI_9750_PM_STATE GENMASK(1, 0) > > - > > #define SDHCI_GLI_9750_CFG2 0x848 > > #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) > > #define GLI_9750_CFG2_L1DLY_VALUE 0x1F > > @@ -149,9 +146,6 @@ > > #define PCI_GLI_9755_MISC 0x78 > > #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) > > > > -#define PCI_GLI_9755_PM_CTRL 0xFC > > -#define PCI_GLI_9755_PM_STATE GENMASK(1, 0) > > - > > #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 > > #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) > > > > @@ -556,11 +550,8 @@ static void gl9750_hw_setting(struct sdhci_host *host) > > sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); > > > > /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ > > - pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value); > > - value |= PCI_GLI_9750_PM_STATE; > > - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); > > - value &= ~PCI_GLI_9750_PM_STATE; > > - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); > > + pci_set_power_state(pdev, PCI_D3hot); > > + pci_set_power_state(pdev, PCI_D0); > > > > /* mask the replay timer timeout of AER */ > > aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); > > @@ -774,11 +765,8 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) > > pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); > > > > /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ > > - pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); > > - value |= PCI_GLI_9755_PM_STATE; > > - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); > > - value &= ~PCI_GLI_9755_PM_STATE; > > - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); > > + pci_set_power_state(pdev, PCI_D3hot); > > + pci_set_power_state(pdev, PCI_D0); > > > > /* mask the replay timer timeout of AER */ > > aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); > > -- > > 2.34.1 > > > >
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 3d5543581537..0f81586a19df 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -25,9 +25,6 @@ #define GLI_9750_WT_EN_ON 0x1 #define GLI_9750_WT_EN_OFF 0x0 -#define PCI_GLI_9750_PM_CTRL 0xFC -#define PCI_GLI_9750_PM_STATE GENMASK(1, 0) - #define SDHCI_GLI_9750_CFG2 0x848 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) #define GLI_9750_CFG2_L1DLY_VALUE 0x1F @@ -149,9 +146,6 @@ #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) -#define PCI_GLI_9755_PM_CTRL 0xFC -#define PCI_GLI_9755_PM_STATE GENMASK(1, 0) - #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) @@ -556,11 +550,8 @@ static void gl9750_hw_setting(struct sdhci_host *host) sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ - pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value); - value |= PCI_GLI_9750_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); - value &= ~PCI_GLI_9750_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); + pci_set_power_state(pdev, PCI_D3hot); + pci_set_power_state(pdev, PCI_D0); /* mask the replay timer timeout of AER */ aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); @@ -774,11 +765,8 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ - pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); - value |= PCI_GLI_9755_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); - value &= ~PCI_GLI_9755_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); + pci_set_power_state(pdev, PCI_D3hot); + pci_set_power_state(pdev, PCI_D0); /* mask the replay timer timeout of AER */ aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);