| Message ID | 20240405-topic-sm8x50-pinctrl-v1-2-92d563c28c90@linaro.org |
|---|---|
| State | Accepted |
| Commit | ba0df20fd3ab0481e5e41e9cb7ba9cbd999549a1 |
| Headers | show |
| Series | qcom: add pinctrl driver for SM8550 and SM8650 | expand |
On Fri, 5 Apr 2024 at 13:45, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > Add pinctrl driver for the TLMM block found in the SM8650 SoC. > > This driver only handles the gpio and qup2_se7 pinmux, and makes sure > the pinconf applies on SDC2 pins. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/pinctrl/qcom/Kconfig | 7 ++++ > drivers/pinctrl/qcom/Makefile | 1 + > drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++++++++++++++++++++++++++++++++++ > 3 files changed, 83 insertions(+) > Acked-by: Sumit Garg <sumit.garg@linaro.org> -Sumit > diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig > index f760bbcdd52..e0196a83e60 100644 > --- a/drivers/pinctrl/qcom/Kconfig > +++ b/drivers/pinctrl/qcom/Kconfig > @@ -48,6 +48,13 @@ config PINCTRL_QCOM_SM8550 > Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC, > as well as the associated GPIO driver. > > +config PINCTRL_QCOM_SM8650 > + bool "Qualcomm SM8650 GCC" > + select PINCTRL_QCOM > + help > + Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, > + as well as the associated GPIO driver. > + > endmenu > > endif > diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile > index 970902e28c8..d83e89ef4f0 100644 > --- a/drivers/pinctrl/qcom/Makefile > +++ b/drivers/pinctrl/qcom/Makefile > @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o > obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o > obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o > obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o > +obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c > new file mode 100644 > index 00000000000..932132fa4a6 > --- /dev/null > +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c > @@ -0,0 +1,75 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Qualcomm sm8650 pinctrl > + * > + * (C) Copyright 2024 Linaro Ltd. > + * > + */ > + > +#include <common.h> > +#include <dm.h> > + > +#include "pinctrl-qcom.h" > + > +#define MAX_PIN_NAME_LEN 32 > +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); > + > +static const struct pinctrl_function msm_pinctrl_functions[] = { > + {"qup2_se7", 1}, > + {"gpio", 0}, > +}; > + > +static const char *sm8650_get_function_name(struct udevice *dev, > + unsigned int selector) > +{ > + return msm_pinctrl_functions[selector].name; > +} > + > +static const char *sm8650_get_pin_name(struct udevice *dev, > + unsigned int selector) > +{ > + static const char *special_pins_names[] = { > + "ufs_reset", > + "sdc2_clk", > + "sdc2_cmd", > + "sdc2_data", > + }; > + > + if (selector >= 210 && selector <= 213) > + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]); > + else > + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); > + > + return pin_name; > +} > + > +static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin, > + unsigned int selector) > +{ > + return msm_pinctrl_functions[selector].val; > +} > + > +static struct msm_pinctrl_data sm8650_data = { > + .pin_data = { > + .pin_count = 214, > + .special_pins_start = 210, > + }, > + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), > + .get_function_name = sm8650_get_function_name, > + .get_function_mux = sm8650_get_function_mux, > + .get_pin_name = sm8650_get_pin_name, > +}; > + > +static const struct udevice_id msm_pinctrl_ids[] = { > + { .compatible = "qcom,sm8650-tlmm", .data = (ulong)&sm8650_data }, > + { /* Sentinel */ } > +}; > + > +U_BOOT_DRIVER(pinctrl_sm8650) = { > + .name = "pinctrl_sm8650", > + .id = UCLASS_NOP, > + .of_match = msm_pinctrl_ids, > + .ops = &msm_pinctrl_ops, > + .bind = msm_pinctrl_bind, > +}; > + > > -- > 2.34.1 >
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f760bbcdd52..e0196a83e60 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -48,6 +48,13 @@ config PINCTRL_QCOM_SM8550 Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_SM8650 + bool "Qualcomm SM8650 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, + as well as the associated GPIO driver. + endmenu endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 970902e28c8..d83e89ef4f0 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o +obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c new file mode 100644 index 00000000000..932132fa4a6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sm8650 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <common.h> +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup2_se7", 1}, + {"gpio", 0}, +}; + +static const char *sm8650_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm8650_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static const char *special_pins_names[] = { + "ufs_reset", + "sdc2_clk", + "sdc2_cmd", + "sdc2_data", + }; + + if (selector >= 210 && selector <= 213) + snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm8650_data = { + .pin_data = { + .pin_count = 214, + .special_pins_start = 210, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm8650_get_function_name, + .get_function_mux = sm8650_get_function_mux, + .get_pin_name = sm8650_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm8650-tlmm", .data = (ulong)&sm8650_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm8650) = { + .name = "pinctrl_sm8650", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; +
Add pinctrl driver for the TLMM block found in the SM8650 SoC. This driver only handles the gpio and qup2_se7 pinmux, and makes sure the pinconf applies on SDC2 pins. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/pinctrl/qcom/Kconfig | 7 ++++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+)