| Message ID | 20240424101503.635364-4-quic_tengfan@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: Add cpufreq and clock support | expand |
On 4/24/2024 7:23 PM, Dmitry Baryshkov wrote: > On Wed, 24 Apr 2024 at 13:17, Tengfei Fan <quic_tengfan@quicinc.com> wrote: >> >> Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply >> clocks to the CPU cores. But this relationship is not represented in DTS >> so far. >> >> So let's make cpufreq node as the clock provider and CPU nodes as the >> consumers. The clock index for each CPU node is based on the frequency >> domain index. > > Is there any reason why this is not a part of the previous patch? Before, I understood that clock and cpufreq support are two functions, so they were divided into two patches. I will squash this patch in cpufreq support patch in the new version patch series. > >> >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> index 92badfd5b0e1..8d75c4f9731c 100644 >> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> @@ -47,6 +47,7 @@ CPU0: cpu@0 { >> device_type = "cpu"; >> compatible = "arm,cortex-a55"; >> reg = <0x0 0x0>; >> + clocks = <&cpufreq_hw 0>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> power-domains = <&CPU_PD0>; >> @@ -72,6 +73,7 @@ CPU1: cpu@100 { >> device_type = "cpu"; >> compatible = "arm,cortex-a55"; >> reg = <0x0 0x100>; >> + clocks = <&cpufreq_hw 0>; >> enable-method = "psci"; >> next-level-cache = <&L2_100>; >> power-domains = <&CPU_PD0>; >> @@ -91,6 +93,7 @@ CPU2: cpu@200 { >> device_type = "cpu"; >> compatible = "arm,cortex-a55"; >> reg = <0x0 0x200>; >> + clocks = <&cpufreq_hw 0>; >> enable-method = "psci"; >> next-level-cache = <&L2_200>; >> power-domains = <&CPU_PD0>; >> @@ -110,6 +113,7 @@ CPU3: cpu@300 { >> device_type = "cpu"; >> compatible = "arm,cortex-a55"; >> reg = <0x0 0x300>; >> + clocks = <&cpufreq_hw 0>; >> enable-method = "psci"; >> next-level-cache = <&L2_300>; >> power-domains = <&CPU_PD0>; >> @@ -129,6 +133,7 @@ CPU4: cpu@400 { >> device_type = "cpu"; >> compatible = "arm,cortex-a55"; >> reg = <0x0 0x400>; >> + clocks = <&cpufreq_hw 0>; >> enable-method = "psci"; >> next-level-cache = <&L2_400>; >> power-domains = <&CPU_PD0>; >> @@ -148,6 +153,7 @@ CPU5: cpu@500 { >> device_type = "cpu"; >> compatible = "arm,cortex-a55"; >> reg = <0x0 0x500>; >> + clocks = <&cpufreq_hw 0>; >> enable-method = "psci"; >> next-level-cache = <&L2_500>; >> power-domains = <&CPU_PD0>; >> @@ -167,6 +173,7 @@ CPU6: cpu@600 { >> device_type = "cpu"; >> compatible = "arm,cortex-a78"; >> reg = <0x0 0x600>; >> + clocks = <&cpufreq_hw 1>; >> enable-method = "psci"; >> next-level-cache = <&L2_600>; >> power-domains = <&CPU_PD0>; >> @@ -186,6 +193,7 @@ CPU7: cpu@700 { >> device_type = "cpu"; >> compatible = "arm,cortex-a78"; >> reg = <0x0 0x700>; >> + clocks = <&cpufreq_hw 1>; >> enable-method = "psci"; >> next-level-cache = <&L2_700>; >> power-domains = <&CPU_PD0>; >> -- >> 2.25.1 >> >> > >
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 92badfd5b0e1..8d75c4f9731c 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -47,6 +47,7 @@ CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; @@ -72,6 +73,7 @@ CPU1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; power-domains = <&CPU_PD0>; @@ -91,6 +93,7 @@ CPU2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; power-domains = <&CPU_PD0>; @@ -110,6 +113,7 @@ CPU3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; power-domains = <&CPU_PD0>; @@ -129,6 +133,7 @@ CPU4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_400>; power-domains = <&CPU_PD0>; @@ -148,6 +153,7 @@ CPU5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_500>; power-domains = <&CPU_PD0>; @@ -167,6 +173,7 @@ CPU6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; power-domains = <&CPU_PD0>; @@ -186,6 +193,7 @@ CPU7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_700>; power-domains = <&CPU_PD0>;
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)