| Message ID | 20240512082858.1806694-7-quic_devipriy@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe support for IPQ9574 | expand |
On Sun, May 12, 2024 at 01:58:58PM +0530, devi priya wrote: > The IPQ9574 platform has 4 Gen3 PCIe controllers: > two single-lane and two dual-lane based on SNPS core 5.70a > > The Qcom IP rev is 1.27.0 and Synopsys IP rev is 5.80a > Added a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0' > which reuses all the members of 'ops_2_9_0' except for the post_init > as the SLV_ADDR_SPACE_SIZE configuration differs between 2_9_0 > and 1_27_0. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: devi priya <quic_devipriy@quicinc.com> > --- > Changes in V5: > - Rebased on top of the below series which adds support for fetching > clocks from the device tree > https://lore.kernel.org/linux-pci/20240417-pci-qcom-clk-bulk-v1-1-52ca19b3d6b2@linaro.org/ > > drivers/pci/controller/dwc/pcie-qcom.c | 36 +++++++++++++++++++++++--- > 1 file changed, 32 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 3d2eeff9a876..af36a29c092e 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -106,6 +106,7 @@ > > /* PARF_SLV_ADDR_SPACE_SIZE register value */ > #define SLV_ADDR_SPACE_SZ 0x10000000 > +#define SLV_ADDR_SPACE_SZ_1_27_0 0x08000000 Can you please explain what this value corresponds to? Even though there is an old value, I didn't get much info earlier on what it is. - Mani > > /* PARF_MHI_CLOCK_RESET_CTRL register fields */ > #define AHB_CLK_EN BIT(0) > @@ -1095,16 +1096,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) > return clk_bulk_prepare_enable(res->num_clks, res->clks); > } > > -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) > +static int qcom_pcie_post_init(struct qcom_pcie *pcie) > { > struct dw_pcie *pci = pcie->pci; > u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > u32 val; > int i; > > - writel(SLV_ADDR_SPACE_SZ, > - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > - > val = readl(pcie->parf + PARF_PHY_CTRL); > val &= ~PHY_TEST_PWR_DOWN; > writel(val, pcie->parf + PARF_PHY_CTRL); > @@ -1144,6 +1142,22 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) > return 0; > } > > +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) > +{ > + writel(SLV_ADDR_SPACE_SZ_1_27_0, > + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > + > + return qcom_pcie_post_init(pcie); > +} > + > +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) > +{ > + writel(SLV_ADDR_SPACE_SZ, > + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); > + > + return qcom_pcie_post_init(pcie); > +} > + > static int qcom_pcie_link_up(struct dw_pcie *pci) > { > u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > @@ -1297,6 +1311,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = { > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */ > +static const struct qcom_pcie_ops ops_1_27_0 = { > + .get_resources = qcom_pcie_get_resources_2_9_0, > + .init = qcom_pcie_init_2_9_0, > + .post_init = qcom_pcie_post_init_1_27_0, > + .deinit = qcom_pcie_deinit_2_9_0, > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > +}; > + > static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; > @@ -1334,6 +1357,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { > .no_l0s = true, > }; > > +static const struct qcom_pcie_cfg cfg_1_27_0 = { > + .ops = &ops_1_27_0, > +}; > + > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1603,6 +1630,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, > { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, > { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, > + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 }, > { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, > { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, > { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 3d2eeff9a876..af36a29c092e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -106,6 +106,7 @@ /* PARF_SLV_ADDR_SPACE_SIZE register value */ #define SLV_ADDR_SPACE_SZ 0x10000000 +#define SLV_ADDR_SPACE_SZ_1_27_0 0x08000000 /* PARF_MHI_CLOCK_RESET_CTRL register fields */ #define AHB_CLK_EN BIT(0) @@ -1095,16 +1096,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) return clk_bulk_prepare_enable(res->num_clks, res->clks); } -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +static int qcom_pcie_post_init(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; int i; - writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); - val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1144,6 +1142,22 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) +{ + writel(SLV_ADDR_SPACE_SZ_1_27_0, + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); + + return qcom_pcie_post_init(pcie); +} + +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +{ + writel(SLV_ADDR_SPACE_SZ, + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); + + return qcom_pcie_post_init(pcie); +} + static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1297,6 +1311,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */ +static const struct qcom_pcie_ops ops_1_27_0 = { + .get_resources = qcom_pcie_get_resources_2_9_0, + .init = qcom_pcie_init_2_9_0, + .post_init = qcom_pcie_post_init_1_27_0, + .deinit = qcom_pcie_deinit_2_9_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; @@ -1334,6 +1357,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { .no_l0s = true, }; +static const struct qcom_pcie_cfg cfg_1_27_0 = { + .ops = &ops_1_27_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1603,6 +1630,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },