@@ -515,6 +515,7 @@ else
fi
ARCH=
+host_mttcg_support=
# Normalise host CPU name and set ARCH.
# Note that this case should only have supported host CPUs, not guests.
case "$cpu" in
@@ -526,6 +527,7 @@ case "$cpu" in
;;
x86_64|amd64)
cpu="x86_64"
+ host_mttcg_support=yes
;;
armv*b|armv*l|arm)
cpu="arm"
@@ -5614,6 +5616,10 @@ if test "$pthread_setname_np" = "yes" ; then
echo "CONFIG_PTHREAD_SETNAME_NP=y" >> $config_host_mak
fi
+if test "$host_mttcg_support" = "yes" ; then
+ echo "CONFIG_MTTCG_HOST=y" >> $config_host_mak
+fi
+
if test "$tcg_interpreter" = "yes"; then
QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/tci $QEMU_INCLUDES"
elif test "$ARCH" = "sparc64" ; then
@@ -5726,6 +5732,7 @@ target_dir="$target"
config_target_mak=$target_dir/config-target.mak
target_name=$(echo $target | cut -d '-' -f 1)
target_bigendian="no"
+target_mttcg_support="no"
case "$target_name" in
armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
@@ -5783,11 +5790,13 @@ case "$target_name" in
TARGET_ARCH=arm
bflt="yes"
gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"
+ target_mttcg_support="yes"
;;
aarch64)
TARGET_BASE_ARCH=arm
bflt="yes"
gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"
+ target_mttcg_support="yes"
;;
cris)
;;
@@ -5938,6 +5947,9 @@ if test "$target_bigendian" = "yes" ; then
fi
if test "$target_softmmu" = "yes" ; then
echo "CONFIG_SOFTMMU=y" >> $config_target_mak
+ if test "$target_mttcg_support" = "yes" ; then
+ echo "CONFIG_MTTCG_TARGET=y" >> $config_target_mak
+ fi
fi
if test "$target_user_only" = "yes" ; then
echo "CONFIG_USER_ONLY=y" >> $config_target_mak
@@ -115,3 +115,5 @@ CONFIG_ACPI=y
CONFIG_SMBIOS=y
CONFIG_ASPEED_SOC=y
CONFIG_GPIO_KEY=y
+
+CONFIG_MTTCG_TARGET=y
This enables the multi-threaded system emulation by default for ARMv7 and ARMv8 guests using the x86_64 TCG backend. This means: - The x86_64 TCG backend supports cmpxchg based atomic ops - The x86_64 TCG backend emits barriers for barrier ops And on the guest side: - The ARM translate.c/translate-64.c have been converted to - use MTTCG safe atomic primitives - emit the appropriate barrier ops - The ARM machine has been updated to - hold the BQL when modifying shared cross-vCPU state - defer cpu_reset to async safe work Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- configure | 12 ++++++++++++ default-configs/arm-softmmu.mak | 2 ++ 2 files changed, 14 insertions(+) -- 2.10.1