Message ID | 20240102-j7200-pcie-s2r-v6-9-4656ef6e6d66@bootlin.com |
---|---|
State | New |
Headers | show |
Series | Add suspend to ram support for PCIe on J7200 | expand |
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 98484f001562..9af4fd64c1f9 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -52,6 +52,7 @@ struct j721e_pcie { u32 mode; u32 num_lanes; u32 max_lanes; + struct gpio_desc *reset_gpio; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -508,6 +509,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n"); goto err_get_sync; } + pcie->reset_gpio = gpiod; ret = cdns_pcie_init_phy(dev, cdns_pcie); if (ret) {