diff mbox series

[RISU,v2,7/8] sparc64: Add a few logical insns

Message ID 20240522034442.140293-8-richard.henderson@linaro.org
State Superseded
Headers show
Series ELF and Sparc64 support | expand

Commit Message

Richard Henderson May 22, 2024, 3:44 a.m. UTC 
Just a token to verify the script is working.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 sparc64.risu | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 sparc64.risu
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Patch

diff --git a/sparc64.risu b/sparc64.risu
new file mode 100644
index 0000000..b45ea86
--- /dev/null
+++ b/sparc64.risu
@@ -0,0 +1,30 @@ 
+###############################################################################
+# Copyright (c) 2024 Linaro Limited
+# All rights reserved. This program and the accompanying materials
+# are made available under the terms of the Eclipse Public License v1.0
+# which accompanies this distribution, and is available at
+# http://www.eclipse.org/legal/epl-v10.html
+###############################################################################
+
+# Input file for risugen defining Sparc64 instructions
+.mode sparc64
+
+ADD_r           SPARC 10 rd:5 0 cc:1 ci:1 000 rs1:5 0 00000000 rs2:5 \
+    !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); }
+ADD_i           SPARC 10 rd:5 0 cc:1 ci:1 000 rs1:5 1 imm:13 \
+    !constraints { reg_ok($rd) && reg_ok($rs1); }
+
+AND_r           SPARC 10 rd:5 0 cc:1 0001 rs1:5 0 00000000 rs2:5 \
+    !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); }
+AND_i           SPARC 10 rd:5 0 cc:1 0001 rs1:5 1 imm:13 \
+    !constraints { reg_ok($rd) && reg_ok($rs1); }
+
+OR_r           SPARC 10 rd:5 0 cc:1 0010 rs1:5 0 00000000 rs2:5 \
+    !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); }
+OR_i           SPARC 10 rd:5 0 cc:1 0010 rs1:5 1 imm:13 \
+    !constraints { reg_ok($rd) && reg_ok($rs1); }
+
+XOR_r           SPARC 10 rd:5 0 cc:1 0011 rs1:5 0 00000000 rs2:5 \
+    !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); }
+XOR_i           SPARC 10 rd:5 0 cc:1 0011 rs1:5 1 imm:13 \
+    !constraints { reg_ok($rd) && reg_ok($rs1); }