diff mbox series

[RISU] risugen/arm: Refine prefetch and memory hintspace patterns

Message ID 20240529173625.800102-1-richard.henderson@linaro.org
State New
Headers show
Series [RISU] risugen/arm: Refine prefetch and memory hintspace patterns | expand

Commit Message

Richard Henderson May 29, 2024, 5:36 p.m. UTC 
Avoid prefetch patterns that are UNPREDICTABLE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 thumb.risu | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Comments

Peter Maydell May 30, 2024, 1:33 p.m. UTC | #1 
On Wed, 29 May 2024 at 18:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Avoid prefetch patterns that are UNPREDICTABLE.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Applied to risu git, thanks.

-- PMM
diff mbox series

Patch

diff --git a/thumb.risu b/thumb.risu
index 357b791..6a05bf2 100644
--- a/thumb.risu
+++ b/thumb.risu
@@ -33,7 +33,20 @@  SMMUL T1 11111 0110 101 rn:4 1111 rd:4 000 r rm:4
 # preload and memory hint space (in the byte and halfword
 # load space, where Rt == 15).
 # The constraint is to avoid UNPREDICTABLE space
-HINTSPACE T1 111 1100 op1:2 0 z 1 y:4 1111 op2:6 any:6 { ($y == 15) || (($op1 & 1) != 0) || !((($op2 & 0x24) == 0x24) || (($op2 & 0x3c) == 0x38)) ; }
+PLD_pi        TI 1111 1000 10 w 1 rn:4 1111 imm:12            { $rn != 0xf; }
+PLD_ni        TI 1111 1000 00 w 1 rn:4 1111 1100 imm:8        { $rn != 0xf; }
+PLD_li        TI 1111 1000 u 00 1 1111 1111 imm:12
+PLD_rr        TI 1111 1000 00 w 1 rn:4 1111 000000 imm:2 rm:4 \
+              { $rn != 0xf && $rm != 0xf; }
+PLI_pi        TI 1111 1001 1 00 1 rn:4 1111 imm:12            { $rn != 0xf; }
+PLI_ni        TI 1111 1001 0 00 1 rn:4 1111 1100 imm:8        { $rn != 0xf; }
+PLI_li        TI 1111 1001 u 00 1 1111 1111 imm:12
+PLI_rr        TI 1111 1001 0 00 1 rn:4 1111 000000 imm:2 rm:4 \
+              { $rn != 0xf && $rm != 0xf; }
+HINTSPACE_rr  T1 1111 1001 0011 rn:4 1111 000000 imm:2 rm:4   { $rn != 0xf; }
+HINTSPACE_ni  T1 1111 1001 0011 rn:4 1111 1100 imm:8          { $rn != 0xf; }
+HINTSPACE_pi  T1 1111 1001 1011 rn:4 1111 imm:12              { $rn != 0xf; }
+HINTSPACE_li  T1 1111 1001 u 011 1111 1111 imm:12
 
 # VMLAL, VMLSL, VQDMLAL, VQDMLSL, VMULL, VQDMULL
 # NB that enc T1 is actually VMLA/VMLS only, T2 is VMLAL/VMLSL only