| Message ID | 20240620104444.5862-23-victorshihgli@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support UHS-II for GL9755 and GL9767 | expand |
On Fri, Jun 21, 2024 at 9:49 AM Ben Chuang <benchuanggli@gmail.com> wrote: > > Hi Victor, > > On Thu, Jun 20, 2024 at 6:46 PM Victor Shih <victorshihgli@gmail.com> wrote: > > > > From: Victor Shih <victor.shih@genesyslogic.com.tw> > > > > Changes are: > > * Enable the internal clock when do reset on UHS-II mode. > > * Increase timeout value before detecting UHS-II interface. > > * Add vendor settings for UHS-II mode. > > > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > > --- > > > > Updates in V17: > > - Use mmc_card_uhs2() to simplify the code in the sdhci_gl9767_reset(). > > - Use mmc_card_uhs2() to simplify the code in the > > sdhci_gl9767_set_power(). > > - Add sdhci_gli_overcurrent_event_enable() to sdhci_gl9767_set_power(). > > > > Updates in V15: > > - Add gl9767 to support uhs2 function. > > > > --- > > > > drivers/mmc/host/sdhci-pci-gli.c | 150 ++++++++++++++++++++++++++++++- > > 1 file changed, 148 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > > index a4164948de81..37c63c45bdc9 100644 > > --- a/drivers/mmc/host/sdhci-pci-gli.c > > +++ b/drivers/mmc/host/sdhci-pci-gli.c > > @@ -210,6 +210,10 @@ > > #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) > > #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) > > > > +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1 0x90C > > +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR GENMASK(31, 29) > > +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE 0x3 > > + > > #define PCIE_GLI_9767_SDHC_CAP 0x91C > > #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) > > > > @@ -228,9 +232,15 @@ > > #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) > > > > #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 > > +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) > > +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL BIT(8) > > #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) > > #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 > > > > +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2 0x948 > > +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING GENMASK(22, 21) > > +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE 0x0 > > + > > #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 > > #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) > > > > @@ -240,6 +250,28 @@ > > #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 > > #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) > > > > +#define PCIE_GLI_9767_UHS2_CTL1 0x95C > > +#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS BIT(5) > > +#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE 0x1 > > +#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL BIT(6) > > +#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE 0x1 > > +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN GENMASK(10, 7) > > +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE 0x3 > > +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV GENMASK(14, 11) > > +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE 0xf > > +#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS GENMASK(16, 15) > > +#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE 0x3 > > +#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV GENMASK(18, 17) > > +#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE 0x0 > > +#define PCIE_GLI_9767_UHS2_CTL1_PDRST BIT(25) > > +#define PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE 0x1 > > + > > +#define PCIE_GLI_9767_UHS2_CTL2 0x964 > > +#define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0) > > +#define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb > > +#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6) > > +#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1 > > + > > #define GLI_MAX_TUNING_LOOP 40 > > > > /* Genesys Logic chipset */ > > @@ -1197,8 +1229,32 @@ static void gl9767_hw_setting(struct sdhci_pci_slot *slot) > > > > static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) > > { > > - sdhci_reset(host, mask); > > - gli_set_9767(host); > > + u16 clk_ctrl; > > + u16 ctrl2; > > + > > + if (mmc_card_uhs2(host->mmc)) { > > + /* need internal clock */ > > + if (mask & SDHCI_RESET_ALL) { > > + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); > > + clk_ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > > + > > + if ((ctrl2 & SDHCI_CTRL_V4_MODE) && (ctrl2 & SDHCI_CTRL_UHS2_ENABLE)) { > > + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); > > + } else { > > + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); > > + sdhci_wait_clock_stable(host); > > + sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); > > + } > > + } > > + if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) > > Is this your intention? > -> if ((mask & SDHCI_RESET_CMD) | > (mask & SDHCI_RESET_DATA)) > sorry, fix typo -> if ((mask & SDHCI_RESET_CMD) || (mask & SDHCI_RESET_DATA)) Best regards, Ben Chuang > > > + sdhci_gli_uhs2_reset_sd_tran(host); > > + > > + sdhci_uhs2_reset(host, mask); > > + gli_set_9767(host); > > + } else { > > + sdhci_reset(host, mask); > > + gli_set_9767(host); > > + } > > } > > > > static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) > > @@ -1288,6 +1344,88 @@ static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) > > return 0; > > } > > > > +static void gl9767_vendor_init(struct sdhci_host *host) > > +{ > > + struct sdhci_pci_slot *slot = sdhci_priv(host); > > + struct pci_dev *pdev = slot->chip->pdev; > > + u32 value; > > + > > + gl9767_vhs_write(pdev); > > + > > + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, &value); > > + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR, > > + PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE); > > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, value); > > + > > + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value); > > + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING, > > + PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE); > > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, value); > > + > > + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, &value); > > + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS, > > + PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) | > > + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL, > > + PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE) | > > + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN, > > + PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE) | > > + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV, > > + PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE) | > > + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS, > > + PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE) | > > + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV, > > + PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE) | > > + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRST, > > + PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE); > > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, value); > > + > > + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); > > + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC, > > + PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE) | > > + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL, > > + PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE); > > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); > > + > > + gl9767_vhs_read(pdev); > > +} > > + > > +static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) > > +{ > > + struct sdhci_pci_slot *slot = sdhci_priv(host); > > + struct pci_dev *pdev; > > + u32 value; > > + > > + pdev = slot->chip->pdev; > > + > > + if (mmc_card_uhs2(host->mmc)) { > > + gl9767_vhs_write(pdev); > > + > > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); > > + value |= PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | > > + PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL; > > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); > > + > > + gl9767_vhs_read(pdev); > > + > > + sdhci_gli_overcurrent_event_enable(host, false); > > + sdhci_uhs2_set_power(host, mode, vdd); > > + sdhci_gli_overcurrent_event_enable(host, true); > > + } else { > > + gl9767_vhs_write(pdev); > > + > > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); > > + value &= ~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | > > + PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL); > > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); > > + > > + gl9767_vhs_read(pdev); > > + > > + sdhci_gli_overcurrent_event_enable(host, false); > > + sdhci_set_power(host, mode, vdd); > > + sdhci_gli_overcurrent_event_enable(host, true); > > + } > > +} > > + > > static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) > > { > > struct sdhci_host *host = slot->host; > > @@ -1324,6 +1462,7 @@ static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot) > > host->mmc->caps2 |= MMC_CAP2_SD_EXP; > > host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; > > sdhci_enable_v4_mode(host); > > + gl9767_vendor_init(host); > > > > return 0; > > } > > @@ -1827,12 +1966,19 @@ static const struct sdhci_ops sdhci_gl9767_ops = { > > .reset = sdhci_gl9767_reset, > > .set_uhs_signaling = sdhci_set_uhs_signaling, > > .voltage_switch = sdhci_gl9767_voltage_switch, > > + .dump_uhs2_regs = sdhci_uhs2_dump_regs, > > + .set_timeout = sdhci_uhs2_set_timeout, > > + .irq = sdhci_uhs2_irq, > > + .set_power = sdhci_gl9767_set_power, > > + .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, > > }; > > > > const struct sdhci_pci_fixes sdhci_gl9767 = { > > .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, > > .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, > > .probe_slot = gli_probe_slot_gl9767, > > + .add_host = sdhci_pci_uhs2_add_host, > > + .remove_host = sdhci_pci_uhs2_remove_host, > > .ops = &sdhci_gl9767_ops, > > #ifdef CONFIG_PM_SLEEP > > .resume = sdhci_pci_gli_resume, > > -- > > 2.25.1 > >
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index a4164948de81..37c63c45bdc9 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -210,6 +210,10 @@ #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1 0x90C +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR GENMASK(31, 29) +#define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE 0x3 + #define PCIE_GLI_9767_SDHC_CAP 0x91C #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) @@ -228,9 +232,15 @@ #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL BIT(8) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2 0x948 +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING GENMASK(22, 21) +#define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE 0x0 + #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) @@ -240,6 +250,28 @@ #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) +#define PCIE_GLI_9767_UHS2_CTL1 0x95C +#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS BIT(5) +#define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE 0x1 +#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL BIT(6) +#define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE 0x1 +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN GENMASK(10, 7) +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE 0x3 +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV GENMASK(14, 11) +#define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE 0xf +#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS GENMASK(16, 15) +#define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE 0x3 +#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV GENMASK(18, 17) +#define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE 0x0 +#define PCIE_GLI_9767_UHS2_CTL1_PDRST BIT(25) +#define PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE 0x1 + +#define PCIE_GLI_9767_UHS2_CTL2 0x964 +#define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0) +#define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb +#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6) +#define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1 + #define GLI_MAX_TUNING_LOOP 40 /* Genesys Logic chipset */ @@ -1197,8 +1229,32 @@ static void gl9767_hw_setting(struct sdhci_pci_slot *slot) static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) { - sdhci_reset(host, mask); - gli_set_9767(host); + u16 clk_ctrl; + u16 ctrl2; + + if (mmc_card_uhs2(host->mmc)) { + /* need internal clock */ + if (mask & SDHCI_RESET_ALL) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + clk_ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + if ((ctrl2 & SDHCI_CTRL_V4_MODE) && (ctrl2 & SDHCI_CTRL_UHS2_ENABLE)) { + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); + } else { + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); + sdhci_wait_clock_stable(host); + sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); + } + } + if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) + sdhci_gli_uhs2_reset_sd_tran(host); + + sdhci_uhs2_reset(host, mask); + gli_set_9767(host); + } else { + sdhci_reset(host, mask); + gli_set_9767(host); + } } static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) @@ -1288,6 +1344,88 @@ static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) return 0; } +static void gl9767_vendor_init(struct sdhci_host *host) +{ + struct sdhci_pci_slot *slot = sdhci_priv(host); + struct pci_dev *pdev = slot->chip->pdev; + u32 value; + + gl9767_vhs_write(pdev); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, &value); + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR, + PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, value); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value); + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING, + PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, value); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, &value); + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS, + PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL, + PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN, + PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV, + PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS, + PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV, + PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRST, + PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, value); + + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); + value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC, + PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE) | + FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL, + PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE); + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); + + gl9767_vhs_read(pdev); +} + +static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) +{ + struct sdhci_pci_slot *slot = sdhci_priv(host); + struct pci_dev *pdev; + u32 value; + + pdev = slot->chip->pdev; + + if (mmc_card_uhs2(host->mmc)) { + gl9767_vhs_write(pdev); + + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); + value |= PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | + PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL; + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); + + gl9767_vhs_read(pdev); + + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_uhs2_set_power(host, mode, vdd); + sdhci_gli_overcurrent_event_enable(host, true); + } else { + gl9767_vhs_write(pdev); + + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); + value &= ~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | + PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL); + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); + + gl9767_vhs_read(pdev); + + sdhci_gli_overcurrent_event_enable(host, false); + sdhci_set_power(host, mode, vdd); + sdhci_gli_overcurrent_event_enable(host, true); + } +} + static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) { struct sdhci_host *host = slot->host; @@ -1324,6 +1462,7 @@ static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot) host->mmc->caps2 |= MMC_CAP2_SD_EXP; host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; sdhci_enable_v4_mode(host); + gl9767_vendor_init(host); return 0; } @@ -1827,12 +1966,19 @@ static const struct sdhci_ops sdhci_gl9767_ops = { .reset = sdhci_gl9767_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .voltage_switch = sdhci_gl9767_voltage_switch, + .dump_uhs2_regs = sdhci_uhs2_dump_regs, + .set_timeout = sdhci_uhs2_set_timeout, + .irq = sdhci_uhs2_irq, + .set_power = sdhci_gl9767_set_power, + .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, }; const struct sdhci_pci_fixes sdhci_gl9767 = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = gli_probe_slot_gl9767, + .add_host = sdhci_pci_uhs2_add_host, + .remove_host = sdhci_pci_uhs2_remove_host, .ops = &sdhci_gl9767_ops, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_gli_resume,