diff mbox series

[2/2] cpufreq/amd-pstate: Fix the scaling_min/max_freq setting on shared memory CPPC systems

Message ID 20240625134127.4464-3-Dhananjay.Ugwekar@amd.com
State New
Headers show
Series AMD Pstate driver fixes | expand

Commit Message

Dhananjay Ugwekar June 25, 2024, 1:41 p.m. UTC 
On shared memory CPPC systems, with amd_pstate=active mode, the change
in scaling_min/max_freq doesn't get written to the shared memory
region. Due to this, the writes to the scaling_min/max_freq sysfs file
don't take effect. Fix this by propagating the scaling_min/max_freq
changes to the shared memory region.

Fixes: ffa5096a7c33 ("cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors")
Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
---
 drivers/cpufreq/amd-pstate.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 9ad62dbe8bfb..7c1c96abe5bd 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -264,6 +264,15 @@  static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
 			cpudata->epp_cached = epp;
 	} else {
 		perf_ctrls.energy_perf = epp;
+		perf_ctrls.max_perf = cpudata->max_limit_perf;
+		perf_ctrls.min_perf = cpudata->min_limit_perf;
+		perf_ctrls.desired_perf = 0U;
+
+		ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
+		if (ret) {
+			pr_debug("failed to set min max limits (%d)\n", ret);
+			return ret;
+		}
 		ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
 		if (ret) {
 			pr_debug("failed to set energy perf value (%d)\n", ret);
@@ -1547,6 +1556,7 @@  static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy)
 	}
 
 	WRITE_ONCE(cpudata->cppc_req_cached, value);
+
 	amd_pstate_set_epp(cpudata, epp);
 }